EP80579 Datasheet, PDF (411/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-27. Offset 9Dh: EXSMRC - Extended System Management RAM Control Register
(Sheet 3 of 3)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:0
Offset Start: 9Dh
Offset End: 9Dh
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
02 : 01
00
Bit Acronym
Bit Description
Sticky
TSEG_SZ
T_EN
TSEG Size: Selects the size of the TSEG memory block if
enabled. Memory from the top of DRAM space (TOLM -
TSEG_SZ) to TOLM is partitioned away so that it may only
be accessed by the processor interface and only then when
the SMM bit is set in the request packet. Non-SMM
accesses to this memory region are specially terminated
when the TSEG memory block is enabled. Note that once
D_LCK (See Table 16-28) is set, these bits become Read-
Only.
0 0 (TOLM – 128 k) to TOLM
0 1 (TOLM – 256 k) to TOLM
1 0 (TOLM – 512 k) to TOLM
1 1 (TOLM – 1 M) to TOLM
TSEG Enable: Enabling of SMRAM memory for Extended
SMRAM space only.
0 = SMRAM memory for Extended SMRAM space disabled.
1 = And G_SMRAME =1 and T_EN = 1, the TSEG is
enabled to appear in the appropriate physical address
space.
Once D_LCK (See Table 16-28) is set, this bit becomes
Read-Only.
Bit Reset
Value
00b
0b
Bit Access
RWL
RWL
16.1.1.26 Offset 9Eh: SMRAM - System Management RAM Control Register
The SMRAMC register controls how accesses to Compatible and Extended SMRAM
spaces are treated. The Open, Close, and Lock bits function only when G_SMRAME bit
is set to a 1. Also, the OPEN bit must be reset before the LOCK bit is set.
Table 16-28. Offset 9Eh: SMRAM - System Management RAM Control Register (Sheet 1 of
2)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:0
Offset Start: 9Eh
Offset End: 9Eh
Size: 8 bit
Default: 02h
Power Well: Core
Bit Range
07
06
Bit Acronym
Bit Description
Sticky
Reserved
D_OPEN
Reserved
SMM Space Open:
0 = The SMM space DRAM is not visible
1 = And D_LCK=0, the SMM space DRAM is made visible
even when SMM decode is not active. This is intended
to help BIOS initialize SMM space.
Software must ensure that D_OPEN=1 and D_CLS=1 are
not set at the same time. This bit becomes RO when
D_LCK is set to 1.
Bit Reset
Value
0b
0b
Bit Access
RWL
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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