EP80579 Datasheet, PDF (759/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 19-33. LPC Cycle Types Supported
Cycle Type
Comment
Memory Read
Single: 1 byte only
Memory Write
Single: 1 byte only
I/O Read
1 byte only. breaks up 16- and 32-bit processor cycles into multiple 8-bit transfers.
See Note 1 below.
I/O Write
1 byte only. breaks up 16- and 32-bit processor cycles into multiple 8-bit transfers.
See Note 1 below.
DMA Read
Can be 1, or 2 bytes
DMA Write
Can be 1, or 2 bytes
Bus Master Read
Can be 1, 2, or 4 bytes. (See Note 2 below)
Bus Master Write
Can be 1, 2, or 4 bytes. (See Note 2 below)
Notes:
1.
For memory cycles below 16 MB that do not target enabled firmware hub ranges, performs standard
LPC memory cycles. It only attempts 8-bit transfers. If the cycle appears on PCI as a 16-bit transfer,
it appears as two consecutive 8-bit transfers on LPC. Likewise, if the cycle appears as a 32-bit
transfer on PCI, it appears as four consecutive 8-bit transfers on LPC. If the cycle is not claimed by
any peripheral, it is subsequently aborted, and returns a value of all ones to the processor. This is
done to maintain compatibility with legacy memory cycles where pull-up resistors would keep the bus
high if no device responds.
2.
Bus Master Read or Write cycles must be naturally aligned. For example, a 1-byte transfer can be to
any address. However, the 2-byte transfer must be word aligned (i.e., with an address where A0=0).
A DWord transfer must be DWord aligned (i.e., with an address where A1 and A0 are both 0).
The Low Pin Count (LPC) Interface Specification, Revision 1.1 allows DMA cycles to be
4-bytes in length, but the LPC controller will only allow a maximum of 16-bit transfers.
Additionally, the LPC Specification allows for firmware memory cycles to be 1, 2, or 4
bytes, and in the case of firmware reads, 128 bytes. However, the LPC controller will
only perform 8-bit transfers.
Bus master read or write cycles must be naturally aligned. A 1 byte transfer can be to
any address. A 2-byte transfer must be word aligned (address bit A0 = 0). A 4-byte
transfer must be Dword aligned (address bits A[1:0] = 00).
19.3.3
Aborting a Cycle
The usage of LFRAME# is followed as it is defined in the LPC Specification.
The LPC Controller performs an abort for the following cases (possible failure cases):
• LPC Controller starts a Memory, I/O, or DMA cycle, but no device drives a valid
SYNC after four consecutive clocks.
• LPC Controller starts a Memory, I/O, or DMA cycle, and the peripheral drives an
invalid SYNC pattern.
• A peripheral drives an illegal address when performing bus master cycles.
• A peripheral drives an invalid value.
19.3.4
Memory Cycle Notes
For cycles below 16M and not targeting firmware, the LPC Controller will perform
standard LPC memory cycles. For cycles targeting firmware, firmware memory cycles
are used. For cycles targeting the fixed token, the fixed token format is used. Only 8-bit
transfers are performed. If a larger transfer occurs, the LPC controller will break it into
multiple 8-bit transfers until the request is satisfied.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
759