EP80579 Datasheet, PDF (801/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
21.4.3.4
Decoding Memory Ranges for SPI
The Boot BIOS Destination straps are sampled on the rising edge of PWROK. If the SPI
port is selected, then the Section 19.2.4, “LPC I/O Configuration Registers” on
page 747 to determine what ranges of memory read addresses are forwarded to SPI.
(See Section 3.7 for details of the actual pin(s) used for selecting SPI.) The Feature
space ranges are unique to the FWH flash. However, the feature space can be treated
just like standard memory from an SPI perspective and therefore allow up to 16 MB of
contiguous memory decode. The EP80579 forwards both data and feature space ranges
to the SPI interface (although the BIOS BAR may block the feature space accesses in
situations where the flash size is less than 4 MB). Since there is only one Flash Chip
Enable pin on the EP80579, there is no need to map the various flash ranges to
multiple enables. Of course, in order to utilize 16 MB, the single flash device would
need to support 128 Mbits of data.
The Top Swap mechanism works in the same way that it does on LPC. Address bit 16 is
inverted when Top Swap is enabled for any accesses to the upper two 64 KB blocks.
Also like LPC, the Top Swap functionality does not apply to accesses generated to the
holes below 1 MB. The SPI interface performs the address bit inversion on only the
Direct Memory Read access method; software can control the address directly with the
programmed command access method. The prefetching and caching logic consistently
comprehends the address inversion to avoid delivering bad data. Also, the protection
mechanisms described above observe the address after the inversion logic.
Memory writes to the BIOS memory range are dropped. This forces all of these
potentially harmful cycles to go through the Programmed Commands interface.
Note that Direct Memory Reads to the E0000h-FFFFFh segments are remapped to top
of flash as mentioned previously in section Section 21.4.3.1. This range is not
remapped when using Programmed Accesses.
21.5
BIOS Programming Considerations
21.5.1
SPI Initialization
This section provides a high level description of the steps that the BIOS should take
upon coming out of RESET when using SPI Flash.
1. Boot vector fetch and other initial BIOS reads using Direct Memory Reads (some of
which are 64 byte code reads). Caching is enabled in hardware by default to
improve performance on consecutive reads to the same line.
2. Turn on the SPI Prefetching policy in the LPC Bridge Configuration Space (Offset
DCh: BC: BIOS Control Register). This policy bit is in configuration space to avoid
requiring protected memory space early in the boot process.
3. Copy the various BIOS modules out of the SPI Flash using Direct Memory Reads. It
is assumed that these reads are shorter than 64 bytes and are targeted to
consecutive addresses; hence, the prefetch mechanism improves the performance
of this sequence.
4. Turn off the SPI Prefetch policy.
5. Program opcode registers in order to discover which Flash device is being used.
Four of the six supported Flash devices support the READ ID instruction. Details of
the discovery algorithm are outside the scope of this specification.
6. Disable Future Request, Offset 3022h: SPIC – SPI Control bit 0. Default state is
Future Request enabled.
7. Re-program opcode registers to support specific Flash vendor’s commands. If not
using all of the Opcode Menu and Prefix Opcodes, BIOS should program a “safe”
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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