EP80579 Datasheet, PDF (1496/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.6.5.4
TDBAL – Transmit Descriptor Base Address Low Register
This register contains the lower bits of the 64 bit descriptor base address. The Transmit
Descriptor Base Address must point to a 16B aligned block of data (i.e. the lower 4 bits
are always 0).
Table 37-70. TDBAL: Transmit Descriptor Base Address Low Register
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 3800h
Offset End: 3803h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 3800h
Offset End: 3803h
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 3800h
Offset End: 3803h
Size: 32 bits
Default: XXXXXXX0h
GbE0: Core
Power Well: Gbe1/2:
Core
Bit Range Bit Acronym
Bit Description
31 : 04
03 : 00
TDBAL
0
Transmit Descriptor Base Address Low
Writes are ignored, reads return 0.
Sticky
Bit Reset
Value
X
0h
Bit Access
RW
RV
37.6.5.5
TDBAH – Transmit Descriptor Base Address High Register
This register contains the upper 32 bits of the 64 bit Descriptor base address.
Table 37-71. TDBAH: Transmit Descriptor Base Address High Register
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 3804h
Offset End: 3807h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 3804h
Offset End: 3807h
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 3804h
Offset End: 3807h
Size: 32 bits
Default: XXXXXXXXh
GbE0: Core
Power Well: Gbe1/2:
Core
Bit Range Bit Acronym
Bit Description
31 : 00
TDBAH
Transmit Descriptor Base Address
Note: TDBAH[31:0] must be set to 0.
Sticky
Bit Reset
Value
Bit Access
X
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
1496
August 2009
Order Number: 320066-003US