EP80579 Datasheet, PDF (656/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.6.1.2
Offset 04h: CSR0 - Channel 0 Channel Status Register
The Channel Status Register (CSR) contains status flags that indicate the channel
status. The register is read by application software to get the current channel status
and to examine the source of an interrupt. Table 16-298 shows the format for the CSR.
Table 16-298.Offset 04h: CSR0 - Channel 0 Channel Status Register (Sheet 1 of 2)
Description:
View: PCI
BAR: EDMALBAR
Bus:Device:Function: 0:1:0
Offset Start: 04h
Offset End: 07h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 : 06
05
04
03
02
Bit Acronym
Bit Description
Sticky
Reserved
CACTV
DABRT
DSTP
DSUS
Reserved
Channel Active:
0 = Channel is inactive and available to be configured
for DMA transfer by software.
1 = Set by the IMCH, indicates the channel is in use
and actively performing DMA data transfers.
The channel active flag is set by the IMCH when:
• Software initiates a DMA transfer by setting the
Start bit of CCR and the DMA channel in response
loads the chain descriptor from the local system
memory
• Software initiates a DMA transfer by setting the
Channel Resume bit of the CCR and the NDAR/
NDUAR point to a legal non-null address in memory.
Aborted:
0 = Software clears this bit by writing a 1 to the bit
location.
1 = Indicates that the current DMA transfer for this
channel encountered an unrecoverable error. If the
Aborted Interrupt Enable bit in the DCR is set, this
generates an interrupt to the processor. Software
polls this bit if an interrupt is not enabled. Error
details are logged in the DMA_FERR and
DMA_NERR registers.
Stopped:
0 = Software clears this bit by writing a 1 to the bit
location.
1 = Indicates that the current transfer for this channel
has been stopped by software setting the Stop bit
in the CCR. If the Stopped Interrupt Enable bit in
the DCR is set, this generates an interrupt to the
processor. Software can use this bit for polling if
interrupts are not enabled.
Suspended:
0 = Cleared when software clears the Suspend bit in
the CCR.
1 = Indicates that the current transfer for this channel
has been stopped by software setting the Suspend
bit in the CCR. If the Suspended Interrupt Enable
bit in the DCR is set, this generates an interrupt to
the processor. Software can use this bit for polling
if interrupts are not enabled.
Bit Reset
Value
0000000h
0b
0b
0b
0b
Bit Access
RO
RWC
RWC
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
656
August 2009
Order Number: 320066-003US