EP80579 Datasheet, PDF (476/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-82. Offset 72h: BUF_NERR - Memory Buffer Next Error Register (Sheet 2 of 2)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:1
Offset Start: 72h
Offset End: 72h
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
02
01
00
Bit Acronym
Bit Description
Sticky
IOPMWB
PMWBSYS
PMWBD
Internal System Bus or I/O to PMWB Parity Error
Detected:
0 = Parity error not detected.
1 = Parity error detected on a line write to PMWB. (NON-
FATAL)
Internal PMWB to System Bus Parity Error Detected:
0 = Parity error not detected.
1 = Parity error detected on data to the System Bus.
(NON-FATAL)
Internal PMWB to DRAM Parity Error Detected:
0 = Parity error not detected.
1= Parity error detected when PMWB is flushed to DRAM.
(NON-FATAL)
Bit Reset
Value
0b
0b
0b
Bit Access
RWC
RWC
RWC
16.2.1.29 Offset 74h: BUF_EMASK - Memory Buffer Error Mask Register
This register masks the unit errors from being recognized. Because they are not
recognized, they are not logged at the unit or global level and no interrupt/messages
are generated.
Table 16-83. Offset 74h: BUF_EMASK - Memory Buffer Error Mask Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:1
Offset Start: 74h
Offset End: 74h
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range Bit Acronym
Bit Description
07 : 04
03
02
01
00
Reserved Reserved
Mask Error bit 03:
BUF_EMASK03 0 = Disable mask.
1 = Enable mask.
Mask Error bit 02:
BUF_EMASK02 0 = Disable mask.
1 = Enable mask.
Mask Error bit 01:
BUF_EMASK01 0 = Disable mask.
1 = Enable mask.
Mask Error bit 00:
BUF_EMASK00 0 = Disable mask.
1 = Enable mask.
Sticky
Bit Reset
Value
0b
Bit Access
0b
RW
0b
RW
0b
RW
0b
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
476
August 2009
Order Number: 320066-003US