EP80579 Datasheet, PDF (147/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 5-8.
Summary of IMCH EDMA Error Conditions
Event
Type
Fatality^a
Reports via^b
Notes
Destination
Address Error
Uncorrectable
Parity Error
Uncorrectable
Write Error
Uncorrectable
Non-Fatal
Non-Fatal
Non-Fatal
SCI, MCERR,
SMI, or SERR
Destination address does not comply
with destination type or range for
channels 0-3.
SCI, MCERR, Parity error during read of source data
SMI, or SERR from system memory for channels 0-3.
SCI, MCERR, Write to RO descriptor registers when
SMI, or SERR DMA in normal mode for channels 0-3.
a. Fatal versus non-fatal classification for reporting through GLOBAL_FERR and GLOBAL_NERR.
b. Based on EDMA_SCICMD, EDMA_SMICMD, EDMA_SERRCMD, and EDMA_MCERRCMD register values.
Table 5-9 summarizes the capabilities of the EDMA error handling for each of the
features that the unit is expected to provide.
Table 5-9.
Summary of IMCH EDMA Error Reporting Capabilities
Feature
Implementation
Enabling and
Masking Error
Reporting
The EDMA_EMASK, EDMA_SCICMD, EDMA_SMICMD, EDMA_SERRCMD, and
EDMA_MCERRCMD registers enables and masks error reporting.
The PCICMD register also enables and masks SERR signals.
Logging Details
EDMA does not capture error logging information beyond the event flags in the
EDMA_FERR, EDMA_NERR and PCISTS.
Reporting Multiple The EDMA_NERR register captures “next” errors. This register indicates up to one
Errors
additional error (beyond the first error) of each type.
Data Poisoning EDMA passes along error information to poison data.
For additional discussion on the IMCH responses to transactions from the EDMA engine,
see Section 10.1, “Overview” and Section 10.2, “IMCH Responses to EDMA
Transactions”.
5.3.8
Unit-Level Errors from PCI Express* Ports A0 and A1
The IMCH PCI Express* Port Controllers capture error events from the port A0 and A1
controllers in per-port registers. The register set provides two parallel error reporting
mechanisms, one that reports standard errors defined by the PCI Express*
specification and a second that reports errors that are specific to the EP80579 PCI
Express* implementation (and thus, outside of the standard PCI Express* errors).
The PCI Express* controllers capture errors required by the PCI Express* base
specification in the UNCERRSTS and CORERRSTS registers. The controllers capture
EP80579-specific errors in the PEAUNITERR register. The errors from both sets of
errors are aggregated in the PEAFERR and PEANERR registers. The PCI Express*
controllers report an error event to the IA-32 core through IA SCI, SMI, SERR, or
MCERR signals based on the settings in the PEAERRDOCMD register.
Table 5-10 summarizes the error conditions that the PCI-Express can generate.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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