EP80579 Datasheet, PDF (156/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 5-26. Summary of Gigabit Ethernet MAC Error Conditions
Event
Type
Fatality^a
Reports via^b
Notes
Statistic Register
ECC Error
Internal Memory
Error
DMA Packet Buffer
Error
DMA Tx Desc. ECC
Error
DMA Rx Desc. ECC
Error
Uncorrectable
Uncorrectable
Uncorrectable
Uncorrectable
Uncorrectable
Fatal
Fatal
Fatal
Fatal
Fatal
ERR, FN0, or Double-bit ECC error in a statistic
FN1 Interrupts register.
ERR, FN0, or Parity or double-bit ECC error in an
FN1 Interrupts internal memory.
ERR, FN0, or Double-bit ECC error during read from
FN1 Interrupts DMA packet buffer on Tx or Rx.
ERR, FN0, or Double-bit ECC error during read from
FN1 Interrupts DMA transmit descriptor.
ERR, FN0, or Double-bit ECC error during read from
FN1 Interrupts DAM receive descriptor.
a. “Fatal” events result in data loss or data corruption that the unit cannot repair, “Non-Fatal” events do not.
b. Based on settings in IMS0, IMS1, and IMS2 registers.
Table 5-27 summarizes the capabilities of the Gigabit Ethernet MAC error handling for
each of the features that the unit is expected to provide.
Table 5-27. Summary of Gigabit Ethernet MAC Error Reporting Capabilities
Feature
Implementation
Enabling and
Masking Error
Reporting
The IMS0, IMS1, and IMS2 interrupt mask set registers and the IMC0, IMC1, and IMC2
interrupt mask clear registers support error enabling and masking.
When software configures the GbE to deliver errors on their own interrupt, the SMIA and
SMME registers from the signal target capability in the PCI configuration header for a GbE
MAC can also support error enabling and masking.
Logging Details
The SINT register from the signal target capability in the PCI configuration header for a
GbE MAC provides read-only access to the state of the interrupt signals from a GbE MAC.
Additional logging information is not captured for the other errors in Table 5-26.
Reporting Multiple Individual status bits in the GbE ICR0, ICR1, and ICR2 interrupt cause registers are set as
Errors
conditions occur. The unit can indicate at most one outstanding error at any time.
Data Poisoning GbE passes along error information to poison data.
See Section 37.6, “GbE Controller Register Summary” and Section 37.5.12, “Error
Handling” for additional details.
5.6.2
CAN Interface
The CAN units signal error conditions through two interrupt signals. The CAN unit
shares one interrupt between functional signaling duties (e.g., signaling that a message
was received) and error reporting, while the second interrupt reports only parity errors.
Status and enable registers in the CAN operate and control signaling functionality in the
CAN such as error reporting.
Table 5-28 summarizes the error conditions that the CAN captures.
Intel^® EP80579 Integrated Processor Product Line Datasheet
156
August 2009
Order Number: 320066-003US