EP80579 Datasheet, PDF (951/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
25.1.1.16 USBREN - USB Resume Enable Register
Note:
There is no support for wake from USB when in S3/S4/S5.
Table 25-17. USBREN - USB Resume Enable Register
Description:
Size: 8 bit
Default: 00h
Power Well: Resume
Bit Range
07 : 02
01
00
Bit Acronym
Bit Description
Sticky
Reserved
PORT1EN
PORT0EN
Reserved
0 = The USB controller will not look at this port for a
wakeup event.
1 = Enables port 1 of the USB controller to look at wakeup
events. When set, the USB controller will monitor port
1 for remote wakeup and connect/disconnect events.
0 = The USB controller will not look at this port for a
wakeup event.
1 = Enables port 0 of the USB controller to look at wakeup
events. When set, the USB controller will monitor port
0 for remote wakeup and connect/disconnect events.
Bit Reset
Value
0h
0h
0h
Bit Access
RW
RW
25.1.1.17 USBCWP - USB Core Well Policy Register
Table 25-18. USBCWP - USB Core Well Policy Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:29:0
Offset Start: C8h
Offset End: C8h
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07 : 01
00
Bit Acronym
Bit Description
Sticky
Reserved
SBMSPEN
Reserved
Static Bus Master Status Policy Enable:
0 = The UHCI Host Controller dynamically sets the Bus
Master status bit based on the memory accesses that
are scheduled. See Section 25.5 for details.
1 = The UHCI host controller statically forces the Bus
Master Status bit in power management space to 1
whenever the HCHalted bit is cleared.
Bit Reset
Value
0h
0h
Bit Access
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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