EP80579 Datasheet, PDF (516/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.3.1.21 Offset A8h: EDMA_SERRCMD - EDMA SERR Command Register
This register enables various errors to generate an SERR special cycle to the IICH.
When an error flag is set in the EDMA_FERR or EDMA_NERR registers, it generates an
SERR, SMI, or SCI special cycle when enabled in the SERRCMD, SMICMD, or SCICMD
registers, or a MCERR# on the FSB when enabled in the MCERRCMD, respectively. Note
that only one message type can be enabled. All channels are expected to use the same
reporting structure, so only one 8-bit register is implemented.
Table 16-133.Offset A8h: EDMA_SERRCMD - EDMA SERR Command Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:1:0
Offset Start: A8h
Offset End: A8h
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range Bit Acronym
Bit Description
Sticky
Descriptor Address Type/Range Error SERR Enable:
Generate SERR if bit 7, 15, 23, or 31 is set in any of the
07
SERR_DSCPER _{EDMA_FERR or EDMA_NERR registers.}
R
0 = Disable
1 = Enable
Descriptor Address Alignment Error SERR Enable:
Generate SERR if bit 6, 14, 22, or 30 is set in any of the
06
SERR_DSCPAE ^{EDMA_FERR or EDMA_NERR registers.}
0 = Disable
1 = Enable
Source Address Type/Range Error SERR Enable:
Generate SERR if bit 5, 13, 21, or 29 is set in any of the
05
SERR_SRCERR ^{EDMA_FERR or EDMA_NERR registers.}
0 = Disable
1 = Enable
04
Reserved Reserved
Destination Address Type/Range Error SERR Enable:
Generate SERR if bit 3, 11, 19, or 27 is set in any of the
03
SERR_DSTERR ^{EDMA_FERR or EDMA_NERR registers.}
0 = Disable
1 = Enable
02
Reserved Reserved
Memory Data Parity Error SERR Enable: Generate
SERR if bit 1, 9, 17, or 25 is set in any of the EDMA_FERR
01
SERR_MDPE1 ^{or EDMA_NERR registers.}
0 = Disable
1 = Enable
Illegal Write Error SERR Enable: Generate SERR if bit 0,
8, 16, or 24 is set in any of the EDMA_FERR or
00
SERR_IWE ^{EDMA_NERR registers.}
0 = Disable
1 = Enable
Bit Reset
Value
0b
0b
0b
0b
0b
0b
0b
0b
Bit Access
RW
RW
RW
RW
RW
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
516
August 2009
Order Number: 320066-003US