EP80579 Datasheet, PDF (932/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
24.8.2.3 Offset 10h: SSTS: Slave Status Register
Table 24-49. Offset 10h: SSTS: Slave Status Register
Description:
View: PCI
Size: 8 bit
BAR: SM_BASE (IO)
Default: 00h
Bus:Device:Function: 0:31:3
Offset Start: 10h
Offset End: 10h
Power Well: Resume^a
Bit Range Bit Acronym
Bit Description
Sticky
Bit Reset
Value
Bit Access
07 : 01
00
Reserved
HOST_
NOTIFY_
STS
Reserved
Software reads this bit to determine that the source of
the interrupt or SMI# was the reception of the Host
Notify Command. Software clears this bit after reading
any information needed from the notify address and
data registers by writing a 1 to this bit. The CMI allows
the notify address and data registers to be overwritten
once this bit has been cleared. When this bit is 1,the
CMI will NACK the first byte (host address) of any new
“Host Notify” commands on the SMLink. Writing a 0 to
this bit has no effect
0 = Bit is clear, allows the notify address and data
registers to be overwritten.
1 = This bit is set when the CMI has completely
received a successful Host Notify Command on the
SMLink pins.
0h
0h
RWC
a. This register is in the resume well and is reset by CF9 RESET or RSMRST#. All bits in this register are implemented in the
64 kHz clock domain. Therefore, software must poll the register until a write takes effect before assuming that a write has
completed internally.
24.8.2.4 Offset 11h: SCMD: Slave Command Register
Table 24-50. Offset 11h: SCMD: Slave Command Register (Sheet 1 of 2)
Description:
View: PCI
Size: 8 bit
BAR: SM_BASE (IO)
Default: 00h
Bus:Device:Function: 0:31:3
Offset Start: 11h
Offset End: 11h
Power Well: Resume^a
Bit Range
07 : 03
02
01
Bit Acronym
Bit Description
Sticky
Reserved Reserved
0 = Allows the generation of interrupt or SMI#.
1 = Software sets this bit to 1 to block the generation
of the interrupt or SMI# due to the SMBALERT#
SMBALERT_DIS
source. This bit is logically inverted and ANDed with
the SMBALERT_STS bit. The resulting signal is
distributed to the SMI# and/or interrupt generation
logic. This bit does not effect the wake logic.
HOST_
NOTIFY_
WKEN
Software sets this bit to 1 to enable the reception of a
Host Notify command as a wake event. When enabled
this event is ORed with the other SMBus wake events
and is reflected in the SMB_WAK_STS bit of the General
Purpose Event 0 Status register.
0 = Disable
1 = Enable
Bit Reset
Value
00h
0h
0h
Bit Access
RW
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
932
August 2009
Order Number: 320066-003US