EP80579 Datasheet, PDF (893/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
23.7.1.1
23.7.1.2
When switching from one mode to another (via MAP.SMS), the BIOS should ensure that
LBAR and ABAR configuration register at offset 20h and 24h are cleared correctly. The
BIOS should also ensure that the function disable bits are set or cleared correctly.
Note that when CC.SCC is not 01h, software could also 'change mode' from IDE to
AHCI or vice versa by writing to the AE bit of GHC register. This change of software
mode during run-time (by using AHCI device driver) is not the kind of mode switching
described in this section.
AHCI Mode
AHCI mode has the following requirements/characteristics:
For AHCI:
• Default CC.SCC = 06h
• Default PI = 01h
• Has a unique Device ID
• BAR0 to BAR4 (i.e. PCMDBA, PCTLBA, SCMDBA, SCTLBA and LBAR) are functional.
• BAR5 (i.e. ABAR) is functional as a memory BAR.
• MSI is supported.
• MAP.SMS is 01b for AHCI mode.
• MAP.SMS is not applicable when MAP.MV is 10b, indicating combined-mode, in
mobile SKUs.
• BIOS should program MAP.MV, then only program MAP.SMS to the desired but legal
value.
IDE Mode
• IDE mode has the following requirements/characteristics:
• D31F2 shall have CC.SCC = 01h
• D31F2 shall support both native and legacy I/O access, indicating by a PI register
default value of 8Ah.
• MSI is not supported.
• BAR0 to BAR4 (i.e. PCMDBA, PCTLBA, SCMDBA, SCTLBA and LBAR) are functional.
• BAR5 is functional as an I/O BAR that implements an index/data pair mechanism
for accessing SControl, SError and SStatus registers.
• MAP.SMS must be 00b for IDE mode.
• BIOS should program MAP.MV, then only program MAP.SMS to the desired but legal
value.
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August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
893