EP80579 Datasheet, PDF (1223/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
34.2.2.17 Offset 1Dh: IOL – I/O Limit Register
This register (together with IOLU) specifies the ending I/O address of devices in the
AIOC infrastructure. The range is aligned to a 4k boundary, so address bits [11:0] are
assumed to be FFF.
Table 34-19. Offset 1Dh: IOL: I/O Limit Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:4:0
Offset Start: 1Dh
Offset End: 1Dh
Size: 8 bit
Default: 0
Power Well: Core
Bit Range
07 : 04
03 : 00
Bit Acronym
Bit Description
Sticky
IOL
IOAW
These bits correspond to address bits [15:12] of the I/O
transaction. Address bits [13:16] are matched with IOLU.
The value “1” means that we implement 32-bit I/O space.
Bit Reset
Value
0h
0
Bit Access
RW
RO
34.2.2.18 Offset 1Eh: SECSTA – Secondary Status Register
Table 34-20. Offset 1Eh: SECSTA: Secondary Status Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:4:0
Offset Start: 1Eh
Offset End: 1Fh
Size: 16 bit
Default: 0h
Power Well: Core
Bit Range Bit Acronym
Bit Description
15
14
13
12
11
10 : 09
08
07
06
05
04 : 00
DPE
RSE
RMA
RTA
STA
DST
MDPE
FB2B
RV
MC66
RV
Detected Parity Error
Received System Error
Received Master Abort
Received Target Abort
Signaled Target Abort
DEVSEL Timing
Master Data Parity Error
Fast Back-to-Back Capable
Reserved
66 MHz Capable
Reserved
Sticky
Bit Reset
Value
0h
0h
0h
0h
0h
00b
0h
0h
0h
0h
0h
Bit Access
RO
RO
RO
RO
RO
RO
RO
RO
RV
RO
RV
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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