EP80579 Datasheet, PDF (433/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-46. Offset 64h: DRT1 - DRAM timing Register 1 (Sheet 3 of 4)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:0
Offset Start: 64h
Offset End: 67h
Size: 32 bit
Default: 12110000h
Power Well: Core
Bit Range Bit Acronym
Bit Description
CAS to CAS Delay
Sticky
Bit Reset
Value
Bit Access
19 :18
tCCD
Encoding
00
10
Others
Number of
CMDCLK
delays
2
4
Reserved
N
00b
RW
Note: set tCCD to 2 clock delay for Burst of 4 (64 bit wide
data interface) or set tCCD to 4 clock delay for Burst of 8
(32 bit wide data interface).
Internal Write to Read command delay, at least 2 x tCK and
independent of operating frequency
JEDEC recommendations for DDR2
400MTS = 10ns
Others = 7.5ns
17 :15
tWTR
Encoding
000
001
010
011
100
101
Others
Number of
CMDCLK
delays
No Delay
1
2
3
4
5
Reserved
N
010b
RW
14 :13
Burst length
BLEN
Encoding
00
01
Burst Length
4
(DDR2 64 bit data
width)
8
(DDR2 32 bit data
width)
N
00b
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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