EP80579 Datasheet, PDF (430/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-45. Offset 78h: DRT0 - DRAM Timing Register 0 (Sheet 7 of 7)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:0
Offset Start: 78h
Offset End: 7Bh
Size: 32 bit
Default: 242AD280h
Power Well: Core
Bit Range
Bit Acronym
Bit Description
Sticky
Programmable Read Pointer Delay: This bit field
determines the read delay, which is based on both DIMM
topology and technology.
The round trip timing budget has been estimated to be
about 11.5 ns. Since an encoding of “000” means less than
one command clock, the encoding values in this table refer
to additional delays beyond one command clock.
Bit Reset
Value
Bit Access
Note that the PRGRPD encoding shown below is for 4 bits.
The 4 bits are formed by concatenating DRT1[0] and
DRT0[2:0].
Please refer to Section 16.1.1.42 for details on the DRT1
register.
2 :00
PRGRPD
PRGRPD[3:0]
Encoding
DRT1[0],
DRT0[2:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
Others
Number of
CMDCLK delays
0
1
2
3
4
5
6
7
8
9
10
Reserved
N
000b
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
430
August 2009
Order Number: 320066-003US