EP80579 Datasheet, PDF (335/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
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12.9.2.6
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12.9.2.8
12.9.2.9
Note:
Source Address Register – SAR
The Source Address Register (SAR) contains the lower 32-bits of the source address for
the current transfer. The SAR is cleared to zero on power-on or system reset and is
loaded automatically with the Source Address field of the chain descriptor (first DWord)
when a new chain descriptor is read from memory. The address can be aligned to any
byte boundary. The system destination for reads to this address range must match the
Source Type setting of the DCR or the transfer will abort.
Source Upper Address Register – SUAR
The upper address will not be used in the EP80579, which is limited to 32-bit
addressing.
The Source Upper Address Register (SUAR) contains the upper 32-bits of the source
address for the current transfer. The SUAR is cleared to zero on power-on or system
reset and is loaded automatically with the Source Upper Address field of the chain
descriptor (second DWord) when a new chain descriptor is read from memory.
Destination Address Register – DAR
The Destination Address Register (DAR) contains the lower 32-bits of the destination
address for the current transfer. The DAR is cleared to zero on power-on or system
reset and is loaded automatically with the Destination Address field of the chain
descriptor (third DWord) when a new chain descriptor is read from memory. The
address can be aligned to any byte boundary. The system destination for writes to this
address range must match the Destination Type setting of the DCR or the transfer will
abort.
Destination Upper Address Register – DUAR
The upper address will not be used in the EP80579, which is limited to 32-bit
addressing.
The Destination Upper Address Register (DUAR) contains the upper 32-bits of the
destination address for the current transfer. The DUAR is cleared to zero on power-on
or system reset and is loaded automatically with the Destination Upper Address field of
the chain descriptor (fourth DWord) when a new chain descriptor is read from memory.
Next Descriptor Address Register – NDAR
The Next Descriptor Address Register (NDAR) contains the lower 32-bit address of the
next descriptor chain in the local system memory. The NDAR is cleared to zero on
power-on or system reset and is loaded automatically with the Next Descriptor Address
field of the chain descriptor (fifth DWord) when a new chain descriptor is read from
memory. This address must be aligned to an 8-DWord address boundary. A value of
zero implies the end of chain if the value of Next Descriptor Upper Address (loaded into
the NDUAR) is also zero. Application software writes this register with the address of
the first chain descriptor in memory prior to initiating a transfer.
The application software must make sure that the Start bit in the CCR and the Channel
Active bit in the CSR are clear prior to writing to the NDAR. The IMCH protects this
register from being written when these bits are not clear. If the NDAR and NDUAR are
zero when the Start bit is set, no transfer will be initiated.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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