EP80579 Datasheet, PDF (1505/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.6.6
Note:
Note:
37.6.6.1
Statistical Registers: Detailed Descriptions
The statistics registers generally assume the presence of a system host driver which
has enabled transmit and receive operations between the GbE controller and host
memory. Throughout the descriptions of specific statistics registers, many require the
driver to have enabled transmits enabled (TCTL.EN=1) or receives enabled
(RCTL.EN=1). Some of the registers provide an indication of link activity even when the
driver has transmits or receives disabled.
All statistics registers are cleared when read. It is the responsibility of software to
maintain incremental count variables if statistics are intended to be monitored regularly
for extended periods of time. All registers “stick” at a maximum value of 0xFFFFFFFF
when reached (until cleared by reset or a read) - if accurate statistics are required, it is
expected that software will query statistics at sufficient intervals to avoid reaching
maximum values and failing to count values unexpectedly.
For the receive statistics it should be noted that a packet is indicated as “received” if it
passes the device's filters and is directed towards Receive Packet Buffer memory. A
packet does not have to be received all the way to the driver in order to be counted as
“received”.
Due to divergent paths between interrupt-generation and logging of relevant statistics
counts, it may be possible to generate an interrupt to the system for a noteworthy
event prior to the associated statistics count actually being incremented. This is
extremely unlikely due to expected delays associated with the system interrupt-
collection and ISR delay, but might be observed as an interrupt for which statistics
values do not quite make sense. Hardware guarantees that any event noteworthy of
inclusion in a statistics count will be reflected in the appropriate count within 1 usec; a
small time-delay prior to read of statistics may be necessary to avoid the potential for
receiving an interrupt and observing an inconsistent statistics count as part of the ISR.
CRCERRS – CRC Error Count Register
This register counts the number of receive packets with CRC errors. In order for a
packet to be counted in this register, it must pass MAC address filtering (Broadcast or
Individual-Address/Multicast match) and must be 64B or greater (from <Destination
Address> through <CRC>, inclusively) in length.
Table 37-79. CRCERRS: CRC Error Count Register
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 4000h
Offset End: 4003h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 4000h
Offset End: 4003h
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 4000h
Offset End: 4003h
Size: 32 bits
Default: 00000000h
GbE0: Aux
Power Well: Gbe1/2:
Core
Bit Range Bit Acronym
31 : 00
CRCERRS CRC error count
Bit Description
Sticky
Bit Reset
Value
0h
Bit Access
RC
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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