EP80579 Datasheet, PDF (298/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
11.3.5
DQ/DQS Mapping
The data signal (DQ) to data strobe (DQS) relationship is controlled by the setting in
the DRAM Row Attribute (DRA) registers (see Section 16.1.1.40, “Offset 70h: DRA[0-1]
– DRAM Row [0:1] Attribute Register” for details). Bits 7:6 and 3:2 of these registers
respectively define the device width for the odd and even rows, which is also used in
the mapping of DQS signals to DQ signals.
Table 11-13. DRA Mapping for DQS
Bits
00
01
10
11
Definition
Reserved
x8 DDR
Reserved
Reserved
DQS per DQ
NA
1 DQS strobe per data byte
NA
NA
Table 11-13 shows the mapping of DQS to DQ in general terms. Table 11-14 gives the
exact relationship.
Table 11-14. DQS to DQ Mapping for x8 Devices
x8 devices
DQ Byte
0
1
2
3
4
5
6
7
8
DQS bit
0
1
2
3
4
5
6
7
8
11.3.6
11.4
11.4.1
32-Bit Mode
DQ[31:0] and the associated DQS[3:0] are connected to the DIMMs in 32-bit mode.
Operation in 32-bit mode is invisible to software and on-chip memory controller
interfaces.
DDR2 Features
The DDR2 generation of technology introduces some new features beyond standard
DDR. This section highlights those supported.
Interface Signalling Voltage
The memory controller supports 1.8 V signaling for DDR2-400, DDR2-533, DDR2-667
and DDR2-800 DIMMs.
Intel^® EP80579 Integrated Processor Product Line Datasheet
298
August 2009
Order Number: 320066-003US