EP80579 Datasheet, PDF (827/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
23.1.1.14 Offset 2Ch: SS - Sub System Identifiers Register
This register is initialized to logic 0 by the assertion of PLTRST#. This register can be
written only once after PLTRST# de-assertion.
Table 23-17. Offset 2Ch: SS - Sub System Identifiers Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:2
Offset Start: 2Ch
Offset End: 2Fh
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 : 16
15 : 00
Bit Acronym
Bit Description
SSID
SSVID
Subsystem ID (SSID): This is written by BIOS. No
hardware action taken on this value.
Subsystem Vendor ID (SSVID): This is written by
BIOS. No hardware action taken on this value.
Sticky
Bit Reset
Value
Bit Access
0000h
RWO
0000h
RWO
23.1.1.15 Offset 34h: CAP – Capabilities Pointer Register
Table 23-18. Offset 34h: CAP – Capabilities Pointer Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:2
Offset Start: 34h
Offset End: 34h
Size: 8 bit
Default: 80h
Power Well: Core
Bit Range
07 : 00
Bit Acronym
Bit Description
Sticky
Capability Pointer (CP): If CC.SCC=01h, then CAP is set
to offset 70h to indicate that the first capability pointer is
CP
the PCI Power Management capability. If CC.SCC is not set
to 01h, then CAP is set to offset 80h to indicate that the
first capability pointer is the Message Signaled Interrupt
capability.
Bit Reset
Value
80h
Bit Access
RO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
827