EP80579 Datasheet, PDF (111/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
3.0
3.1
3.1.1
Platform Memory and Device Configuration
Overview
This chapter presents the views of the major address spaces and device configuration
structures as seen by various internal and external agents. Three related aspects are
covered:
• The memory maps seen by various internal and external agents.
• The endianness seen by various agents and mechanisms the EP80579 uses to allow
communication between agents with different endianness expectations.
• The PCI configuration infrastructure, which the EP80579 exposes through its
memory maps.
Configuration Objectives
The EP80579 device and configuration model operates in a system-on-a-chip
environment and blends the architectures of many disparate components into a unified
whole. The major goals for the device configuration and access architecture include:
• Provide a configuration and access model that is aligned with existing IA platform
algorithms.
• Support a unified address space model.
The IA-32 core is the primary agent responsible for device configuration. This is true
across all supported SKUs.
To provide device configuration and operation capabilities that are aligned with the IA
platform, the EP80579 uses the existing PCI infrastructure to expose on-die software-
visible sub-blocks as devices on the PCI fabric. Figure 3-1 presents a logical overview
of this organization.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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