EP80579 Datasheet, PDF (1710/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 43-1. EP80579 TAPs Public Instructions
Public Instruction
MCH TAP Controller
BYPASS
IDCODE
Supported
EP80579 IDCODE; unique per
EP80579 silicon stepping
EXTEST
Boundary Scan for EP80579 IOs
VmC TAP Controller
Supported
IA-32 core IDCODE; fixed for all products
using the core
Implemented, but not connected to any IO
pads
43.1.3
EP80579 JTAG ID Codes
On account of the multiple TAPs, the EP80579 supports and displays multiple IDCODEs.
This is described below in Table 43-2.
Table 43-2. EP80579 TAP IDCode Values
JTAG TAP
Controller
IDCode
IMCH
(EP80579)
32’h0E66_0013
IA-32 Core 32’h0B36_0013
Comments
The 4 MSBs are incremented for each EP80579 silicon stepping
(major or minor)
Fixed for all products and steppings using this core
43.1.4
Special Requirements and Limitations
The JTAG implementation has the following requirements for proper JTAG operation.
• For proper boundary scan operation, the following GbE reset pins need to be in the
specified states: SYS_PWR_OK = 1 and AUX_PWR_GOOD = 1. This
requirement is true even if the GbE units are disabled. These additional non-JTAG
pins must be automatically driven to the proper values by the platform's power-up
devices when the EP80579 is powered up for boundary scan testing.
• Several high-speed interfaces and critical system reset and power related pins have
been removed from the Boundary Scan chain. These are documented in Section
43.2.1, “JTAG Boundary Scan”.
43.1.5
JTAG Instructions Summary: MCH
The table in this section summarizes the EP80579-specific JTAG instructions
implemented in the MCH section of the chip.
The JTAG instructions are classified as follows:
• Public: These instructions are available to anyone.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1710
August 2009
Order Number: 320066-003US