EP80579 Datasheet, PDF (958/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 25-23. USBSTS: USB Status Register (Sheet 2 of 2)
Description:
View: PCI
BAR: USBIOBAR (IO)
Bus:Device:Function: 0:29:0
Offset Start: 02h
Offset End: 03h
Size: 16 bit
Default: 0020h
Power Well: Core
Bit Range
02
01
00
Bit Acronym
Bit Description
Sticky
RSM_DET
USBEINT
USBINT
Resume Detect:
0 = Resume not detected.
1 = The host controller received a “RESUME” signal
from a USB device. This is only valid if the Host
controller is in a global suspend state (bit 3 of
Command register = 1).
Software clears this bit by writing a 1 to it.
USB Error Interrupt: The Host Controller sets this bit
to 1 when completion of a USB transaction results in an
error condition (e.g., error counter underflow). If the TD
on which the error interrupt occurred also had its IOC
bit set, both this bit and Bit 0 are set.
0 = No USB Error Interrupt.
1 = Completion of a USB transaction results in an error
condition (e.g., error counter underflow). If the TD
on which the error interrupt occurred also had its
IOC bit set, both this bit and Bit 0 are set.
Software clears this bit by writing a 1 to it.
USB Interrupt:
0 = No USB interrupt.
1 = The Host Controller sets this bit to 1 when the
cause of an interrupt is a completion of a USB
transaction whose Transfer Descriptor had its IOC
bit set. The Host Controller also sets this bit to 1
when a short packet is detected (actual length field
in TD is less than maximum length field in TD), and
short packet detection is enabled in that TD.
Software clears this bit by writing a 1 to it.
Bit Reset
Value
0h
0h
0h
Bit Access
RWC
RWC
RWC
25.2.1.3
USBINTR: USB Interrupt Enable Register
This register enables and disables reporting of the corresponding interrupt to the
software. When a bit is set and the corresponding interrupt is active, an interrupt is
generated to the host. Fatal errors (Host Controller Processor Error-bit 4, USBSTS
Register) cannot be disabled by the host controller. Interrupt sources that are disabled
in this register still appear in the Status Register to allow the software to poll for
events.
Intel^® EP80579 Integrated Processor Product Line Datasheet
958
August 2009
Order Number: 320066-003US