EP80579 Datasheet, PDF (101/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 1-4. Glossary Table (Sheet 4 of 5)
Term
Metastability
Multi Media Timer (MMT)
Non-Coherent
North
Ordering
Outbound
OWord
Packet
PCI Reset
Peer-to-Peer
Platform Reset
Plesiochronous
Port
Posted
Push Model
Queue
Receiver
Request
Reserved
Resume Power Well
Resume Reset
RTC Power Well
Definition
A characteristic of flip flops that describes the state where the output becomes non-
deterministic. Most commonly caused by a setup or hold time violation.
See High Precision Event Timer (HPET) in Table 1-3.
Transactions that may cause the processor’s view of memory through the cache to be different
than that obtained through the I/O subsystem.
Usually refers to bridges. The bridge or device that is closer to the processor-memory complex.
Refers to the order in which signals and/or memory accesses to different locations must reach
global visibility to ensure some behavior. Note that this excludes the “ordering” necessary to
prevent data hazards which are accesses to the same location.
A transaction where the request destination is I/O and is sourced from the processor-memory
complex. The terms Inbound and Outbound refer to transactions as a whole and never to
Requests or Completions in isolation. (For example, an Outbound Read generates Upstream
data, whereas an Outbound Write has Downstream data. Even more confusing, the Completion
to an Outbound Read travels Upstream.)
128 bits of data on a naturally aligned sixteen-byte boundary (e.g., the least significant four
bits of the byte address are b”0000”). This is the native size of the IMCH datapath.
The indivisible unit of data transfer and routing, consisting of a header, data, and CRC.
PCIRST#. This is the secondary PCI Bus reset signal. It is a logical OR of the primary interface
PLTRST# signal and the state of the Secondary Bus Reset bit.
Transactions that occur between two devices independent of memory or the processor.
IICH asserts PLTRST# to reset devices that reside on the primary PCI bus. The IICH asserts
PLTRST# during power-up and when a hard reset sequence is initiated through the CF9h
register. PLTRST# is driven inactive a minimum of 1 ms after both PWROK and VRMPWRGD are
driven high. PLTRST# is driven for a minimum of 1 ms when initiated through the CF9h
register.
From Greek, meaning almost synchronous. Describes signals that have the same nominal
digital rate, but are synchronized on different clocks. Any variation in rate is constrained within
specified limits, which allows a device to process the data signal without buffer underflow or
overflow by making periodic compensating adjustments that repeat or delete dummy data bits.
However, there is no limit to the phase difference that can accumulate between the signals over
time.
1. Logically, an interface between a component and a PCI Express* Link.
2. Physically, a group of Transmitters and Receivers located on the same chip that define a
Link.
A Transaction that is considered complete by the initiating agent or source before it actually
completes at the Target of the Request or destination. All agents or devices handling the
Request on behalf of the original Initiator must then treat the Transaction as being system
visible from the initiating interface all the way to the final destination. Commonly refers to
memory writes.
Method of messaging or data transfer that predominately uses writes instead of reads.
A first-in first-out (FIFO) structure.
1. The Agent that receives a Packet across an interface regardless of whether it is the ultimate
destination of the packet. 2. More narrowly, the circuitry required to convert incoming signals
from the physical medium to more perceptible forms.
A packet, phase, or cycle used to initiate a Transaction on a interface, or within a component.
The contents or undefined states or information that are not defined at this time. Using any
reserved area is not permitted. Reserved register bits must be set to 0. However, when stated,
there may be specific instances where a reserved register is either non-zero, or there may be a
requirement to make it non-zero.
Trickle from power supply, only turns off when power is disconnected from wall.
Signal that resets the parts of the IICH in the resume power well, generated when the trickle
supply turns on.
Powered by a coin cell battery and only turns off when the battery is drained. Powers the RTC
and some resume events.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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