EP80579 Datasheet, PDF (1016/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
26.3.2.9
Note:
Note:
Note:
Offset 64h: PORTSC - Port N Status and Control Register
A host controller must implement one or more port registers. Software uses the N_Port
information from the Structural Parameters Register to determine how many ports
need to be serviced. All ports have the structure defined below. Software must not
write to unreported Port Status and Control Registers.
This register is in the suspend power well. It is only reset by hardware when the
suspend power is initially applied or in response to a host controller reset. The initial
conditions of a port are:
• No device connected
• Port disabled
When a device is attached, the port state transitions to the connected state and system
software will process this as with any status change notification. Refer to Section 4 of
the EHCI Specification for operational requirements for how change events interact
with port suspend mode.
If a port is being used as the Debug Port, then the port may report device connected
and enabled when the Configured Flag is a zero.
There is no support for wake from USB when in S3/S4/S5.
Table 26-48. Offset 64h: PORTSC - Port N Status and Control Register (Sheet 1 of 5)
Description: Port 1 64 - 67h, Port 2 68 - 6Bh
View: PCI
BAR: MBAR
Bus:Device:Function: 0:29:7
Offset Start: 64h
Offset End: 67h
View: PCI
BAR: MBAR
Bus:Device:Function: 0:29:7
Offset Start: 68h
Offset End: 6Bh
Size: 32 bit
Default: 00003000h
Power Well: Suspend
Bit Range
31 :23
22
21
Bit
Acronym
Bit Description
Sticky
Reserved Reserved.
WKOC_E
Wake on Overcurrent Enable:
0 = Disable. (Default).
1 = Writing this bit to a one enables the port to be sensitive
to overcurrent conditions as wake-up events. When
enabled to do so, the EHC sets the PME Status bit in the
Power Management Control/Status Register (offset 54,
bit 15) when the overcurrent Active bit (bit 4 of this
register) is set.
Note: There is no support for wake from USB when in S3/S4/
S5.
Wake on Disconnect Enable:
0 = Disable. (Default).
1 = Writing this bit to a one enables the port to be sensitive
to device disconnects as wake-up events. When enabled
WKDSCNNT
_E
to do so, the EHC sets the PME Status bit in the Power
Management Control/Status Register (offset 54, bit 15)
when the Current Connect Status changes from
connected to disconnected (i.e., bit 0 of this register
changes from 1 to 0).
Note: There is no support for wake from USB when in S3/S4/
S5.
Bit Reset
Value
000h
0h
0h
Bit Access
RW
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
1016
August 2009
Order Number: 320066-003US