EP80579 Datasheet, PDF (902/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
24.2.1.11 Offset 2Eh: SID: Subsystem Identification Register
BIOS sets the value in this register to identify the Subsystem ID. The SMBus SID
register, in combination with the SMBus SVID register, enables the operating system to
distinguish each subsystem from the others.
Note:
The software can write to this register only once per core well reset. Writes must be
done as a single 16-bit cycle.
Table 24-13. Offset 2Eh: SID: Subsystem Identification Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:3
Offset Start: 2Eh
Offset End: 2Fh
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range
15 : 00
Bit Acronym
Bit Description
Sticky
Subsystem ID: The SID register, in combination with the
SVID register, enables the operating system (OS) to
SID
distinguish subsystems from each other.
Note: Software can write to this register only once per
core well reset. Writes must be done as a single
16-bit cycle.
Bit Reset
Value
00h
Bit Access
RWO
24.2.1.12 Offset 3Ch: INTLN: Interrupt Line Register
Table 24-14. Offset 3Ch: INTLN: Interrupt Line Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:3
Offset Start: 3Ch
Offset End: 3Ch
Size: 8 bit
Default: 00h
Power Well: Resume
Bit Range Bit Acronym
Bit Description
07 : 00
INTLN
Interrupt line: This data is not used. It is used to
communicate to software the interrupt line that the
interrupt pin is connected to PIRQB#.
Sticky
Bit Reset
Value
Bit Access
00h
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
902
August 2009
Order Number: 320066-003US