EP80579 Datasheet, PDF (282/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
BIOS and SMM code must cooperate to properly configure the IMCH in order to ensure
reliable operation of the SMM function.
10.5.1.2
SMM Space Definition
SMM space is defined by both its addressed SMM space and its DRAM SMM space. The
addressed SMM space is defined as the range of FSB addresses used by the IA-32 core
to access SMM space. DRAM SMM space is defined as the range of physical DRAM
memory locations containing SMM information.
The SMM space can be accessed at one of three transaction address ranges:
• Compatible
• High
• TSEG
The Compatible and TSEG SMM space is not remapped and therefore the addressed
and DRAM SMM physical addresses are identical. The High SMM space is remapped;
thus the addressed and DRAM SMM locations are different. Note that the High DRAM
space is the same as the Compatible Transaction Address space.
Table 10-16 describes all three unique addressing combinations:
• Compatible Transaction Address
• High Transaction Address
• TSEG Transaction Address
Table 10-16. Supported SMM Ranges
SMM Space Enabled
Transaction Address Space (Adr)
DRAM Space (DRAM)
Compatible (C)
A0000h to BFFFFh
A0000h to BFFFFh
High (H)
0FEDA0000h to 0FEDBFFFFh
A0000h to BFFFFh
TSEG (T)
(TOLM-TSEG_SZ) to TOLM
(TOLM-TSEG_SZ) to TOLM
Notes:
1.
High SMM: This implementation is consistent with the Intel E7500 and Intel E7501 designs. In prior
MCH designs the High segment was the 384 Kbyte region from A_0000h to F_FFFFh. However
C_0000h to F_FFFFh was not useful, so it has been deleted in the IMCH design.
2.
TSEG SMM: This implementation is consistent with the Intel E7500 and Intel E7501 designs. In prior
MCH designs the TSEG address space was offset by 256 MBytes to allow for simpler decoding and the
TSEG was remapped to just under the TOLM. In the IMCH the TSEG region is not offset by 256 MBytes
and it is not remapped.
3.
In Cases where DRAM TOLM is less than TOM TSEG cannot be used for SMM. For this case MENC
memory spans consecutive space from above TOLM to below TOLM and will conflict with TSEG space
Intel^® EP80579 Integrated Processor Product Line Datasheet
282
August 2009
Order Number: 320066-003US