EP80579 Datasheet, PDF (722/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
18.2.2.9 Offset 0Eh: TWDS - TCO Watchdog Status Register
Table 18-10. Offset 0Eh: TWDS - TCO Watchdog Status Register
Description:
View: PCI
BAR: TCOBASE (IO)
Bus:Device:Function: 0:31:0
Offset Start: 0Eh
Offset End: 0Eh
Size: 8 bit
Default: 00h
Power Well: Resume
Bit Range
07 : 00
Bit Acronym
Bit Description
Sticky
TWDS
The value written to this register is passed via SMBus to
an External LAN controller. It can be used by the BIOS
or system management software to indicate more
details on the boot progress. The register is reset to 00h
based on a RSMRST# (but not PCI reset).
Bit Reset
Value
00h
Bit Access
RW
18.2.2.10 Offset 10h: LE - Legacy Elimination Register
Table 18-11. Offset 10h: LE - Legacy Elimination Register
Description:
View: PCI
BAR: TCOBASE (IO)
Bus:Device:Function: 0:31:0
Offset Start: 10h
Offset End: 10h
Size: 8 bit
Default: 03h
Power Well: Core
Bit Range
07 : 02
01
00
Bit Acronym
Bit Description
Sticky
Reserved Reserved
0 = When software sets the bit to 0, IRQ12 is low (not
IRQ12_CAUSE
asserted).
1 = When software sets the bit to 1, IRQ12 is high
(asserted).
IRQ1_CAUSE
0 = When software sets the bit to 0, IRQ1 is low (not
asserted).
1 = When software sets the bit to 1, IRQ1 is high
(asserted).
Bit Reset
Value
00h
1
1
Bit Access
RO
RW
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
722
August 2009
Order Number: 320066-003US