EP80579 Datasheet, PDF (1832/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
49.5.1.2
Power Management AC Characteristics
The following table and diagrams illustrate the sequencing that occurs for supported
power state transitions. For more detail, see Section 27.6, “Sleep States”.
Table 49-12. Power Sequencing Signal Timings (Sheet 1 of 2)
Sym
Parameter
Min
Max
Units Notes Fig #
t204 VccSus supplies active to RSMRST# inactive
10
–
ms
7
49-1
t214 Vcc supplies active to PWROK, VRMPWRGD active
99
–
ms
11
49-1,
49-3
t215 Vcc active to STPCLK# and CPUSLP# inactive
–
PWROK and VRMPWRGD/ CPU_VRD_PWR_GD active and SYS_RESET#
t217 inactive to SUS_STAT# inactive and Processor I/F signals latched to 32
strap value.
50
ns
38
RTCCLK
-
49-1,
49-3
1
49-1,
49-3
t218 SUS_STAT# inactive to PLTRST# and PCIRST# inactive
2
3
RTCCLK
49-1,
49-3
t230
VccSus active to SLP_S5#, SLP_S4#, SLP_S3#, SUS_STAT#,
PLTRST# and PCIRST#active
–
50
ns
-
49-1
t231
t232
RSMRST# inactive to SUSCLK running, SLP_S5# inactive
–
110
ms
2
49-1
t233 SLP_S5# inactive to SLP_S4# inactive
See Note 10
10
49-1
t234 SLP_S4# inactive to SLP_S3# inactive
1
2
RTCCLK
1
49-1
t271 S1 Wake Event to CPUSLP# inactive
1
25
PCICLK
8
49-2
SUSCLK duty cycle
30
70
%
9
t280 STPCLK# active to NSI Message
0
PCICLK
3
49-2,
49-3
t281 NSI Message to CPUSLP# active
60
63
PCICLK
8
49-2
t283 NSI Message to SUS_STAT# active
2
RTCCLK
1
49-3
t284 SUS_STAT# active to PLTRST#, PCIRST# active
7
17
RTCCLK
1
49-3
t287 PLTRST#, PCIRST# active to SLP_S3# active
1
t289 SLP_S3# active to PWROK, VRMPWRGD/ CPU_VRD_PWR_GD inactive
0
2
RTCCLK
1
49-3
ms
4
49-3
t291
t294
SLP_S3# active to SLP_S4# active
PWROK, VRMPWRGD/ CPU_VRD_PWR_GD inactive to Vcc supplies
inactive
1
2
RTCCLK
1
49-3
20
ns
6
49-3
t295 SLP_S4# active to SLP_S5# active
1
2
RTCCLK
1, 5
49-3
t296 Wake Event to SLP_S5# inactive
1
10
RTCCLK
1
49-3
Notes:
1.
These transitions are clocked off the internal RTC. 1 RTC clock is approximately 32 µs.
2.
If there is no RTC battery in the system, so VCCPRTC and the VCCPSUS supplies come up together, the delay from
RTCRST# and an inactive RSMRST# prior to SUSCLK toggling may be as much as 2.5 s.
3.
STPCLK# assertion triggers the processor to send a stop grant acknowledge cycle.
4.
The EP80579 has no maximum timing requirement for this transition. It is up to the system designer to determine if the
SLP_S3#, SLP_S4# and SLP_S5# signals are used to control the power planes.
5.
If the transition to S5 is due to Power Button Override, SLP_S3#, SLP_S4# and SLP_S5# are asserted together similar
to timing t287 (PCIRST# active to SLP_S3# active).
6.
VCC in diagram represents all core well supplies that are powered off in S3 state.
7.
VCCSus in diagram represents all sustainable supplies as identified in the Suspend power well.
8.
These transitions are clocked off the 33MHz PCICLK. 1 PCICLK is approximately 30ns.
9.
SUSCLK is an output of the RTC generator (32.768 KHz), has a duty cycle that can be as low as 30% or as high as 70%.
10.
The Min/Max times depend on the programming of the “SLP_S4# Minimum Assertion Width” and the “SLP_S4#
Assertion Stretch Enable bits. Note that this does not apply for synchronous SMI’s.
11.
The relationship that the active edge of SYS_PWR_OK (platform signal connected to PWROK, PWRGD, and
SYS_PWR_OK pins) has to the active edge of VRMPWRGD/ CPU_VRD_PWR_GD in Figure 6-1 must be observed.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1832
August 2009
Order Number: 320066-003US