EP80579 Datasheet, PDF (793/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
21.4.2.5 SPID[0-6] – SPI Data N
Table 21-9. Offset 3030h, 3038h, 3040h, 3048h, 3050h, 3058h, 3060h: SPI[0-6] - SPI
Data [0-6]
Description:
View: PCI
BAR: RCBA
Bus:Device:Function: 0:31:0
Offset Start: 3030h at 4h
Offset End: 306Ch at 4h
Size: 64 bit
Default: 00000000h
Power Well: Core
Bit Range
63 : 00
Bit Acronym
Bit Description
Sticky
SCD
SPI Cycle Data N (SCD[N]): Similar definition as SPI
Cycle Data 0. However, this register does not begin shifting
until SPID[N-1] has completely shifted in/out.
Bit Reset
Value
0
Bit Access
RW
21.4.2.6
Offset 3070h: BBAR – BIOS Base Address
This register is not writable when the SPI Configuration Lock-Down bit in Offset 3020h:
SPIS – SPI Status register is set.
Table 21-10. Offset 3070h: BBAR - BIOS Base Address
Description:
View: PCI
BAR: RCBA
Bus:Device:Function: 0:31:0
Offset Start: 3070h
Offset End: 3073h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 :24
23 :08
7 :00
Bit Acronym
Bit Description
Sticky
Rsvd
BSP
Rsvd
Reserved
Bottom of System Flash: This field determines the
bottom of the System BIOS. The EP80579 will not run
programmed commands nor memory reads whose address
field is less than this value. This field corresponds to bits
23:8 of the 3-byte address; bits 7:0 are assumed to be
00h for this vector when comparing to a potential SPI
address. Software must always program 1’s into the upper,
Don’t Care bits of this field based on the flash size.
Hardware does not know the size of the flash array and
relies upon the correct programming by software. The
default value of 0000h results in all cycles allowed.
Note: The SPI Host Controller prevents any Programmed
cycle using the Address Register with an address less than
the value in this register. Some flash devices specify that
the Read ID command must have an address of 0000h or
0001h. If this command must be supported with these
devices, it must be performed with the BBAR - BIOS Base
Address programmed to 0h. Some of these devices have
actually been observed to ignore the upper address bits of
the Read ID command.
Reserved
Bit Reset
Value
0
0
0
Bit Access
RV
RWS
RV
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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