EP80579 Datasheet, PDF (299/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
11.4.2
On-DIMM Die Termination (ODT)
The JEDEC DDR2 DRAM Specification requires that DDR2 DIMM devices provide
selectable on-DieDIMM Termination (ODT) as an alternative to traditional discrete
termination on the motherboard. The On-DIMM termination ODT feature is enabled via
the DDR extended memory register select (EMRS) command ODTENA and supports
both 75 and 150 terminations activated dynamically via dedicated On-DIMM
termination ODT interface signals on the DIMM.
The EP80579 implements two ODT pins to control the behavior of the termination on
the two ranks of DRAM devices. The mapping of the CS & ODT pins for the various
DIMM configurations is shown in Table 11-6. The behavior of these ODT signals can
controlled by setting the appropriate bits in the Section 16.1.1.49, “Offset B0h:
DDR2ODTC - DDR2 ODT Control Register”.
The EP80579 controls operation of DDR2 devices with or without on-DIMMDie
termination enabled, but is verified by Intel only in On-Die (ODT) enabled mode of
operation. ODT can be disabled by setting the appropriate bits in DRAMODT bit in
Section 16.1.1.43, “Offset 7Ch: DRC – DRAM Controller Mode Register”.
Table 11-15 shows the ODT related timing parameters.
The EP80579 supports operation of DDR2 devices with or without on-DIMMDie
termination enabled, but is verified by Intel only in the On-Die (ODT) enabled mode of
operation. ODT can be disabled by setting the DRAMODT bit in Section 16.1.1.43,
“Offset 7Ch: DRC – DRAM Controller Mode Register”.
Table 11-15. ODT Timing Parameters
Parameter
Description
Value
tCK
Clock Period
5, 3.75, 3, 2.5ns
tOND
ODT turn on delay
2 tCK
tOFD
ODT turn off delay
2.5 tCK
CL
CAS Latency
3, 4, 5, 6
RL
Read Latency
CL
WL
Write Latency (RL - 1)
CL - 1
BL
Burst Length
4, 8
ODT_RD_on
Assertion of ODT pin to inactive slot during = RL - tOND - 1
reads
= RL - 3
ODT_RD_ontime Time for which the ODT pin is asserted
= tOND+1+BL/2+0.5-tONF
= 2+1+BL/2+0.5-2.5
= BL/2+1
ODT_WR_on
Assertion of ODT pin to inactive slot during = WL - tOND - 1
writes
= WL - 3
ODT_WR_ontime Time for which the ODT pin is asserted
= tOND+1+BL/2+0.5-tONF
= 2+1+BL/2+0.5-2.5
= BL/2+1
• For WL = 2 (CL = 3), the ODT_WR_on = -1. This requires the controller to enable ODT 1 tCK before the
Write command is issued. EP80579 memory controller will not support asserting the ODT pin before it
issues the write command. The result is that for CL=3, the termination in the inactive slot will be turned
on at the same time the DQ bus is being driven by the memory controller.
• The ODT turn on and off timings will be calculated by the hardware based on the DRAM configuration
parameters: CL and BL.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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