EP80579 Datasheet, PDF (454/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-67. Offset 44h: GLOBAL_NERR - Global Next Error Register (Sheet 2 of 2)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:1
Offset Start: 44h
Offset End: 47h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
11
10
09
08
07 : 00
Bit Acronym
Bit Description
Sticky
NSI Non-Fatal Error: This bit is sticky through reset.
System software clears this bit by writing a 1 to the
NSI_NFE ^location.
Y
0 = No non-fatal NSI error.
1 = The IMCH detected a non-fatal NSI error.
DMA Controller Non-Fatal Error Device 1 non-fatal
error (EDMA): This bit is sticky through reset. System
DMA_NFE ^{software clears this bit by writing a 1 to the location.}
Y
0 = No non-fatal DMA Controller error.
1 = The IMCH detected a non-fatal DMA Controller error.
PCI Express Port A(0) Non-Fatal Error: This bit is
sticky through reset. System software clears this bit by
writing a 1 to the location.
PA_NFE
0 = No non-fatal PCI Express Port A error.
Y
1 = The IMCH detected a non-fatal PCI Express Port A
error.
PCI Express Port A1 Non-Fatal Error: This bit is sticky
through reset. System software clears this bit by writing a
1 to the location.
PA1_NFE _{0 = No non-fatal PCI Express Port A1 error.}
Y
1 = The IMCH detected a non-fatal PCI Express Port A1
error.
Reserved Reserved
Bit Reset
Value
0b
0b
0b
0b
0b
Bit Access
RWC
RWC
RWC
16.2.1.14 Offset 48h: NSI_FERR - NSI First Error Register
NSI errors for NSI port to IICH. These errors include errors detected on the NSI link,
errors from the NSI hierarchy, and errors internal to the NSI unit.
Table 16-68. Offset 48h: NSI_FERR - NSI First Error Register (Sheet 1 of 3)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:1
Offset Start: 48h
Offset End: 4Bh
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 : 30
29
28
Bit Acronym
Bit Description
Reserved
UR
Reserved
Reserved
Unsupported Request: This bit is sticky through reset.
0 = Cleared by writing a ‘1’ to the bit location.
1 = Unsupported Request detected.
Reserved
Sticky
Bit Reset
Value
0b
0b
0b
Bit Access
RWC
Intel^® EP80579 Integrated Processor Product Line Datasheet
454
August 2009
Order Number: 320066-003US