EP80579 Datasheet, PDF (442/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.1.1.47 Offset 8Dh: CKEDIS - CKE Clock Disable Register
This register is used to enable or disable the CKE pins to the DIMMS.
Also see Section 16.1.1.43, “Offset 7Ch: DRC – DRAM Controller Mode Register” CSR
that describes the CKEPNM bit that can force the CKE[1:0] pins low.
Table 16-51. Offset 8Dh: CKEDIS - CKE Clock Enable Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:0
Offset Start: 8Dh
Offset End: 8Dh
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range Bit Acronym
Bit Description
7 :03
02 02
Reserved
CKE1DIS
Reserved
CKE1 Disable (Sticky)
Bit corresponds CKE[1] pin. Default is enabled.
1 = Disable CKE[1] signals
0 = Enable CKE[1] signals.
Sticky
N
Bit Reset
Value
00000b
Bit Access
RO
Y
0b
RW
01 01
00 00
Reserved
CKE0DIS
When disabled, the CKE[1] pin is tristated.
Reserved
CKE0 Disable (Sticky)
Bit controls CKE[0] pin. Default is enabled.
1 = Disable CKE[0] signals
0 = Enable CKE[0] signals.
N
0b
RO
Y
0b
RW
When disabled, the CKE[0] pin is tristated.
Intel^® EP80579 Integrated Processor Product Line Datasheet
442
August 2009
Order Number: 320066-003US