EP80579 Datasheet, PDF (587/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-211.Offset 140h: PEAUNITERR - PCI Express Unit Error Register (Sheet 2 of 2)
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 140h
Offset End: 143h
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 140h
Offset End: 143h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
11
10
09
08
07
06
05
04
03
02
01
00
Bit Acronym
Bit Description
Sticky
0 = Link Down Error [STICKY]: Software clears this bit
LDE
by writing a ‘1’ to the bit position.
1 = Set when the link transitions from DL_UP to
Y
DL_DOWN.
Downstream Data Queue Parity Error [STICKY]: A
parity error occurred in the downstream data queue.
DDQPE 0 = Software clears this bit by writing a ‘1’ to the bit
Y
position.
1 = Parity error occurred in the downstream data queue.
Reserved Reserved
Reserved Reserved
Reserved Reserved
Reserved Reserved
Reserved Reserved.
Common Block Parity Error [Sticky]:
Indicates that a parity error occurred on a configuration
CommBlkPAR register within the common block.
Y
0 = No parity error
1 = Parity error occurred.
Reserved Reserved.
SMB Clock Low Timeout [STICKY]:.
SMBCLTO
0 = Software clears this bit by writing a ‘1’ to the bit
position.
Y
1 = SMB CLK low greater than 25 ms.
Unexpected NAK on SMB [STICKY]:
UESMBN
0 = Software clears this bit by writing a ‘1’ to the bit
position.
Y
1 = Unexpected NAK on SMB detected.
SMBLA
SMB lost bus arbitration. (Correctable) [STICKY]: This bit
is sticky through reset.
0 = Software clears this bit by writing a ‘1’ to the bit
Y
position.
1 = SMB lost bus arbitration.
Bit Reset
Value
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
Bit Access
RWC
RWC
RWC
RWC
RWC
RWC
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
587