EP80579 Datasheet, PDF (1625/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Figure 41-3. Clock Synchronization
Timestamp
Master
T1
Sync
Slave
T2
Follow_up(T1)
Timestamp
Timestamp
T3
T4
Delay_req
Timestamp
Delay_response(T4)
Table 41-2. Clock Synchronization Protocol Flow
Action
Generate a Sync Packet
Timestamp the Sync packet and store the value in registers (T1)
Timestamp the incoming Sync packet; store the value in a register
(T2); and record the sourceID and sequenceId in registers
Read the timestamp register (T1) and put the value in a Follow_Up
packet and send it.
Note the timestamp (T1) from the received Follow-up message
Generate a Delay_Req packet and send it
Timestamp the outgoing Delay_Req packet and store in register (T3)
Timestamp incoming Delay_Req message; store value (T4); record
sourceID and sequenceID in registers
Read timestamp (T4) from register and send back to slave using a
Delay_Response packet
Note the timestamp (T4) from received Delay_Resp packet and
calculate the time offset using T1, T2, T3, and T4
Responsibility
SW
HW
HW
SW
SW
SW
HW
HW
SW
SW
Node Type
Master
Master
Slave
Master
Slave
Slave
Slave
Master
Master
Slave
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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