EP80579 Datasheet, PDF (892/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
23.6.4.3.4
HBA D3 state
After the interface and device have been put into a low power state, the HBA may be
put into a low power state. This is performed via the PCI power management registers
in configuration space. AHCI only supports the D3 state.
There are two very important aspects to note when using PCI power management.
• When the power state is D3, only accesses to configuration space are allowed. Any
attempt to access the register memory space must result in master abort.
• When the power state is D3, no interrupts may be generated, even if they are
enabled. If an interrupt status bit is pending when the controller transitions to D0,
an interrupt may be generated.
Software must disable interrupts (GHC.IE must be cleared to '0') prior to requesting a
transition of the HBA to the D3 state. This precaution by software avoids an interrupt
storm if an interrupt occurs during the transition to the D3 state.
PxCMD.ST must be cleared to '0' before entry into the D3 power state.
23.6.4.4
PME
When the HBA is in the D3 state, it may optionally wake based on a change in the
device state.
PME must be generated when the HBA is in the D3 state under the following conditions:
• PxIS.PCS is set to '1' due to a native hot plug insertion.
• PxIS.DIS set, indicating an interlock switch has been opened or closed.
• PxIS.CPDS set, indicating cold presence detect state change.
• Set Device Bits FIS received on the interface with the T bit set to ‘1’ and the
Notification (‘N’) bit also set to ‘1’.
If any of these bits are set, regardless of the setting of the enables in PxIE and GHC.IE,
the HBA shall generate PME#.
For the I²C approach, the SGPIO Control Register is made visible in the SMBus slave
register space. SGPIO control register is mapped to SMBus slave registers at offset 9h,
Ah and Bh. The SM Link interface is externally connected to an unused SMBus on the
BMC. BMC will read the data, encapsulate it in the IPMI format and drive that data
through another SMBus or I²C bus to the GEM controller. GEM controller then updates
the LED drivers with the updated status.
23.7
Additional Information
23.7.1
Mode Switching
Software mode could change from one to another by manipulating the MAP register.
There are some specific requirements for the register:
• MAP.SMS and MAP.MV shall only be programmed to values that would result in legal
CC.SCC, DID and PI values (See Section 48.1.5.1). If MAP.SMS and MAP.MV are not
programmed correctly, hardware shall default the mode back to IDE.
• MAP register must survive across D3hot to D0 power state transitions.
• MAP.SMS shall not be manipulated during runtime operation; i.e. the OS will not do
this. However, the BIOS may choose to change it during POST to switch to other
software mode.
Intel^® EP80579 Integrated Processor Product Line Datasheet
892
August 2009
Order Number: 320066-003US