EP80579 Datasheet, PDF (17/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Contents
Register ........................................................................................ 646
16.5.1.66 Offset 298h: WDLL_MISC - DLL Miscellaneous Control ......................... 648
16.6 Memory Mapped I/O for EDMA Registers ............................................................ 651
16.6.1 Register Details ..................................................................................... 653
16.6.1.1 Offset 00h: CCR0 - Channel 0 Channel Control Register ...................... 653
16.6.1.2 Offset 04h: CSR0 - Channel 0 Channel Status Register ....................... 656
16.6.1.3 Offset 08h: CDAR0 - Channel 0 Current Descriptor Address
Register ........................................................................................ 657
16.6.1.4 Offset 0Ch: CDUAR0 - Channel 0 Current Descriptor Upper Address Register
658
16.6.1.5 Offset 10h: SAR0 - Channel 0 Source Address Register ....................... 658
16.6.1.6 Offset 14h: SUAR0 - Channel 0 Source Upper Address Register............. 659
16.6.1.7 Offset 18h: DAR0 - Channel 0 Destination Address Register.................. 659
16.6.1.8 Offset 1Ch: DUAR0 - Channel 0 Destination Upper Address
Register ........................................................................................ 660
16.6.1.9 Offset 20h: NDAR0 - Channel 0 Next Descriptor Address Register ......... 661
16.6.1.10 Offset 24h: NDUAR0 - Channel 0 Next Descriptor Upper
Address Register ............................................................................ 661
16.6.1.11 Offset 28h: TCR0 - Channel 0 Transfer Count Register ......................... 662
16.6.1.12 Offset 2Ch: DCR0 - Channel 0 Descriptor Control Register .................... 663
16.6.1.13 Offset 40h: CCR1 - Channel 1 Channel Control Register ....................... 665
16.6.1.14 Offset 44h: CSR1 - Channel 1 Channel Status Register ........................ 665
16.6.1.15 Offset 48h: CDAR1 - Channel 1 Current Descriptor Address
Register ........................................................................................ 665
16.6.1.16 Offset 4Ch: CDUAR1 - Channel 1 Current Descriptor Upper Address Register
666
16.6.1.17 Offset 50h: SAR1 - Channel 1 Source Address Register ....................... 666
16.6.1.18 Offset 54h: SUAR1 - Channel 1 Source Upper Address Register............. 666
16.6.1.19 Offset 58h: DAR1 - Channel 1 Destination Address Register.................. 667
16.6.1.20 Offset 5Ch: DUAR1 - Channel 1 Destination Upper Address
Register ........................................................................................ 667
16.6.1.21 Offset 60h: NDAR1 - Channel 1 Next Descriptor Address Register.......... 667
16.6.1.22 Offset 64h: NDUAR1 - Channel 1 Next Descriptor Upper
Address Register............................................................................. 668
16.6.1.23 Offset 68h: TCR1 - Channel 1 Transfer Count Register ......................... 668
16.6.1.24 Offset 6Ch: DCR1 - Channel 1 Descriptor Control Register ................... 668
16.6.1.25 Offset 80h: CCR2 - Channel 2 Channel Control Register ....................... 669
16.6.1.26 Offset 84h: CSR2 - Channel 2 Channel Status Register ........................ 669
16.6.1.27 Offset 88h: CDAR2 - Channel 2 Current Descriptor Address
Register ........................................................................................ 669
16.6.1.28 Offset 8Ch: CDUAR2 - Channel 2 Current Descriptor Upper Address Register
670
16.6.1.29 Offset 90h: SAR2 - Channel 2 Source Address Register ....................... 670
16.6.1.30 Offset 94h: SUAR2 - Channel 2 Source Upper Address Register............. 670
16.6.1.31 Offset 98h: DAR2 - Channel 2 Destination Address Register.................. 671
16.6.1.32 Offset 9Ch: DUAR2 - Channel 2 Destination Upper Address
Register ........................................................................................ 671
16.6.1.33 Offset A0h: NDAR2 - Channel 2 Next Descriptor Address Register ......... 671
16.6.1.34 Offset A4h: NDUAR2 - Channel 2 Next Descriptor Upper
Address Register ............................................................................ 672
16.6.1.35 Offset A8h: TCR2 - Channel 2 Transfer Count Register ......................... 672
16.6.1.36 Offset ACh: DCR2 - Channel 2 Descriptor Control Register.................... 672
16.6.1.37 Offset C0h: CCR3 - Channel 3 Channel Control Register ...................... 673
16.6.1.38 Offset C4h: CSR3 - Channel 3 Channel Status Register ........................ 673
16.6.1.39 Offset C8h: CDAR3 - Channel 3 Current Descriptor Address
Register ........................................................................................ 673
16.6.1.40 Offset CCh: CDUAR3 - Channel 3 Current Descriptor Upper Address Register
674
16.6.1.41 Offset D0h: SAR3 - Channel 3 Source Address Register........................ 674
16.6.1.42 Offset D4h: SUAR3 - Channel 3 Source Upper Address Register ............ 674
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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