EP80579 Datasheet, PDF (70/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Contents
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23-70
23-71
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23-74
23-75
23-76
23-77
24-1
24-2
24-3
24-4
24-5
24-6
24-7
24-8
24-9
24-10
24-11
24-12
24-13
24-14
24-15
24-16
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24-18
24-19
24-20
24-21
24-22
24-23
24-24
24-25
24-26
24-27
24-28
24-29
24-30
24-31
24-32
24-33
24-34
24-35
24-36
24-37
24-38
24-39
24-40
24-41
24-42
24-43
Offset 130h: PxSERR[0-1] – Port [0-1] Serial ATA Error Register ........................... 870
Offset 134h: PxSACT[0-1] – Port [0-1] Serial ATA Active Register ......................... 872
Offset 138h: PxCI[0-1] – Port [0-1] Command Issue Register ................................ 872
Offset 13Ch: PxSNTF[0-1] – Port [0-1] SNotification Register ............................... 873
Errors During Non-DATA FIS Reception................................................................ 877
Errors During PIO Data FIS Reception.................................................................. 877
Errors During DMA Data FIS Reception ................................................................ 877
Errors during unknown FIS type3 reception .......................................................... 878
Errors during FIS transmission ........................................................................... 878
MSI vs. PCI IRQ Actions .................................................................................... 882
SMBus signals .................................................................................................. 895
Bus 0, Device 31, Function 3: Summary of SMBus Controller PCI
Configuration Registers ..................................................................................... 896
Offset 00h: VID: Vendor ID Register .................................................................. 897
Offset 02h: DID: Device ID Register .................................................................. 897
Offset 04h: CMD: Command Register ................................................................ 897
Offset 06h: DS – Device Status Register ............................................................ 898
Offset 08h: RID: Revision ID Register ................................................................ 899
Offset 09h: PI: Programming Interface Register .................................................. 900
Offset 0Ah: SCC: Sub Class Code Register ......................................................... 900
Offset 0Bh: BCC: Base Class Code Register ........................................................ 900
Offset 20h: SM_BASE: SMB Base Address Register .............................................. 901
Offset 2Ch: SVID: SVID Register ...................................................................... 901
Offset 2Eh: SID: Subsystem Identification Register ............................................. 902
Offset 3Ch: INTLN: Interrupt Line Register ......................................................... 902
Offset 3Dh: NTPN: Interrupt Pin Register ............................................................ 903
Offset 40h: HCFG: Host Configuration Register ................................................... 903
Offset F8h: MANID: Manufacturer ID Register ..................................................... 904
Bus 0, Device 31, Function 3: Summary of SMBus Controller Configuration Registers
Mapped Through SM_BASE I/O BAR .................................................................... 905
Offset 00h: HSTS: Host Status Register ............................................................. 906
Offset 02h: HCTL: Host Control Register ............................................................ 908
Offset 03h: HCMD: Host Command Register ........................................................ 912
Offset 04h: TSA: Transmit Slave Address Register .............................................. 912
Offset 05h: HD0: Data 0 Register ..................................................................... 913
Offset 06h: HD1: Data 1 Register ..................................................................... 913
Offset 07h: HBD: Host Block Data Register ......................................................... 914
Offset 08h: PEC: Packet Error Check Data Register ............................................. 915
Offset 0Ch: AUXS: Auxiliary Status Register ....................................................... 915
Offset 0Dh: AUXC: Auxiliary Control Register ...................................................... 916
Offset 0Eh: SMLC: SMLINK_PIN_CTL Register ...................................................... 916
Offset 0Fh: SMBC: SMBUS_PIN_CTL Register ...................................................... 917
Quick Protocol .................................................................................................. 919
Send/Receive Byte Protocol without PEC .............................................................. 919
PEC Send/Receive Order.................................................................................... 919
Write Byte/Word Protocol Without PEC ................................................................ 920
PEC Bit Order .................................................................................................. 920
Read Byte/Word Protocol without PEC ................................................................. 921
Read Byte/Word Protocol with PEC ...................................................................... 921
Process Call Protocol without PEC........................................................................ 922
Process Call Protocol with PEC ........................................................................... 923
Block Read/Write Protocol without PEC ............................................................... 924
Block Read/Write Protocol with PEC .................................................................... 925
Block Write-Block Read Process Call Protocol with/without PEC .............................. 927
Summary of Enables for SMBALERT# .................................................................. 929
Intel^® EP80579 Integrated Processor Product Line Datasheet
70
August 2009
Order Number: 320066-003US