EP80579 Datasheet, PDF (1515/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.6.6.20 PRC127 – Good Packets Received Count (65-127 Bytes) Register
This register counts the number of good packets (no link or CRC error) received that
are from 65B-127B (from <Destination Address> through <CRC>, inclusively) in
length. This register includes good regular packets received to the Receive Packet
Buffer. Packets identified as Missed Packets due to Receive Packet Buffer overruns are
not included in this count (refer to the “MPC – Missed Packet Count Register” on
page 1507).
Table 37-98. PRC127: Good Packets Received Count (65-127 Bytes) Register
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 4060h
Offset End: 4063h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 4060h
Offset End: 4063h
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 4060h
Offset End: 4063h
Size: 32 bits
Default: 00000000h
GbE0: Aux
Power Well: Gbe1/2:
Core
Bit Range
31 : 00
Bit Acronym
Bit Description
Sticky
PRC127 Number of good packets received, (65-127) bytes in length
Bit Reset
Value
0h
Bit Access
RC
37.6.6.21 PRC255 – Good Packets Received Count (128-255 Bytes) Register
This register counts the number of good packets (no link or CRC error) received that
are from 128B-255B (from <Destination Address> through <CRC>, inclusively) in
length. This register includes good regular packets received to the Receive Packet
Buffer. Packets identified as Missed Packets due to Receive Packet Buffer overruns are
not included in this count (refer to the “MPC – Missed Packet Count Register” on
page 1507).
Table 37-99. PRC255: Good Packets Received Count (128-255 Bytes) Register
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 4064h
Offset End: 4067h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 4064h
Offset End: 4067h
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 4064h
Offset End: 4067h
Size: 32 bits
Default: 00000000h
GbE0: Aux
Power Well: Gbe1/2:
Core
Bit Range Bit Acronym
Bit Description
31 : 00
PRC255
Number of good packets received, (128-255) bytes in
length.
Sticky
Bit Reset
Value
Bit Access
0h
RC
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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