EP80579 Datasheet, PDF (1484/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 37-59. RXDCTL: Receive Descriptor Control Register (Sheet 2 of 2)
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 2828h
Offset End: 282Bh
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 2828h
Offset End: 282Bh
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 2828h
Offset End: 282Bh
Size: 32 bits
Default: 00010000h
GbE0: Core
Power Well: Gbe1/2:
Core
Bit Range
24
23 : 22
21 : 16
15 : 14
13 : 08
07 : 06
05 : 00
Bit Acronym
Bit Description
Sticky
GRAN
Rsvd
WTHRESH
Rsvd
HTHRESH
Rsvd
PTHRESH
Granularity of the thresholds in this register.
0 = Threshold values are in units of Cache Lines,
thresholds specified must not be greater than 31
descriptors (496B) or 15 32B cache lines.
1 = Threshold values are in units of Descriptors (16B
each)
Reserved
Write-back Threshold. This field controls the write-back
of processed receive descriptors. This threshold refers to
the number of receive descriptors in the GbE hardware
buffer which are ready to be written back to host memory.
In the absence of external events (explicit flushes), the
write-back will occur only after more than WTHRESH
descriptors are available for write-back.
Note: Since the default value for this field is 1, the
descriptors are normally written back as soon as
one cache line is available. This field must contain
a non-zero value to take advantage of the write-
back bursting capabilities of the EP80579’s GbE.
Reserved
Host Threshold. This field is used to control the fetching
of descriptors from host memory. This threshold refers to
the number of valid, unprocessed receive descriptors that
must exist in host memory before they will be fetched.
Reserved
Prefetch Threshold. This field is used to control when a
prefetch of descriptors will be considered. This threshold
refers to the number of valid, unprocessed receive
descriptors the chip has in its GbE hardware buffer. If this
number drops below PTHRESH, the algorithm will consider
pre-fetching descriptors from host memory. This fetch will
not happen however unless there are at least HTHRESH
valid descriptors in host memory to fetch.
Bit Reset
Value
0h
0h
01h
0h
0h
0h
0h
Bit Access
RW
RV
RW
RV
RW
RV
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
1484
August 2009
Order Number: 320066-003US