EP80579 Datasheet, PDF (1115/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
30.0 Interrupts
30.1
Overview
Only level-triggered interrupts can be shared. PCI interrupts (PIRQs) are inherently
shared on the board. These must, therefore, be programmed as level-triggered.
Table 30-1 and Table 30-2 show the mapping of the various interrupts in Non-APIC and
APIC modes. Table 30-3 lists the interrupt signals action in the associated power state
Table 30-1. Interrupt Options - 8259 Mode
IRQ
SERIRQ
Pin
Internal Modules
0
No
No
8254 Counter 0, MMT 0
1
Yes
No
2
No
No
8259 2 cascade only
3
Yes
No
Option for PIRQx
4
Yes
No
Option for PIRQx
5
Yes
No
Option for PIRQx
6
Yes
No
Option for PIRQx
7
Yes
No
Option for PIRQx
8
No
No
RTC, MMT 1
9
Yes
No
Option for PIRQx, SCI, TCO
10
Yes
No
Option for PIRQx, SCI, TCO
11
Yes
No
Option for PIRQx, SCI, TCO, MMT 2
12
Yes
No
Option for PIRQx
13
No
No
FERR# Logic
14
Yes
Yes
PIRQx, SATA Primary (legacy mode)
15
Yes
Yes
PIRQx,
SATA Secondary (legacy mode)
Notes:
1.
If an interrupt is used for PCI IRQ[A:H], SCI, or TCO, it must not be used for ISA (legacy)-style
interrupts (via SERIRQ).
2.
PIRQ[A-D] do not come out on the pins any longer.
3.
In 8259 mode, PCI interrupts are mapped to IRQ3, 4, 5, 6, 7, 9, 10, 11, 12, 14, or 15.
4.
If IRQ11 is used for MMT 2, software must ensure IRQ11 is not shared with any other devices to
guarantee the proper operation of MMT 2. The hardware does not prevent sharing of IRQ11.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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