K60P100M100SF2RM Datasheet, PDF (996/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Functional Description
If (ELSnB:ELSnA = 0:0) when the counter reaches the value in the CnV register, the
CHnF bit is set and the channel (n) interrupt is generated (if CHnIE = 1), however the
channel (n) output is not controlled by FTM.
If (ELSnB:ELSnA = 1:0), then the channel (n) output is forced high at the counter
overflow (when the CNTIN register value is are loaded into the FTM counter), and it is
forced low at the channel (n) match (FTM counter = CnV) (see the following figure).
MOD = 0x0008
CnV = 0x0005
counter
overflow
channel (n)
match
counter
overflow
CNT ... 0 1 2 3 4 5 6 7 8 0 1 2 ...
channel (n) output
CHnF bit
previous value
TOF bit
Figure 39-182. EPWM Signal with ELSnB:ELSnA = 1:0
If (ELSnB:ELSnA = X:1), then the channel (n) output is forced low at the counter
overflow (when the CNTIN register value is loaded into the FTM counter), and it is
forced high at the channel (n) match (FTM counter = CnV) (see the following figure).
MOD = 0x0008
CnV = 0x0005
counter
overflow
channel (n)
match
counter
overflow
CNT ...
channel (n) output
01
2 3 45 6
780
1 2 ...
CHnF bit
previous value
TOF bit
Figure 39-183. EPWM Signal with ELSnB:ELSnA = X:1
If (CnV = 0x0000), then the channel (n) output is a 0% duty cycle EPWM signal and
CHnF bit is not set even when there is the channel (n) match. If (CnV > MOD), then the
channel (n) output is a 100% duty cycle EPWM signal and CHnF bit is not set even when
there is the channel (n) match. Therefore, MOD must be less than 0xFFFF in order to get
a 100% duty cycle EPWM signal.
Note
It is expected that the EPWM mode be used only with CNTIN
= 0x0000.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
996
Freescale Semiconductor, Inc.