K60P100M100SF2RM Datasheet, PDF (517/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 23 Watchdog Timer (WDOG)
23.3 Functional Overview
WDOG
Disable Control/Configuration
bit changes N bus clk cycles after
unlocking
N bus clk cycles
System
Bus Clock
WAITEN
STOPEN
StandbyEN
DebugEN
WDOGEN
WINEN
WDOGT
WDOG
CLKSRC
WDOGTEST
0xC520
0xD928
Unlock Sequence
2 Writes of data within K bus clock
cycles of each other
Allow update for N bus
clk cycles
Window_begin
R
32-bit Modulus Reg
(Time-out Value)
32-bit Timer
0xA602
0xB480
No unlock
after reset
No config
after unlocking
Invalid Refresh
Seq
Refresh
Outside
Window
Timer Time-out
Invalid
Unlock Seq
Refresh Sequence
2 writes of data within K
bus clock cycles of each
other
Interrupt
Y
IRQ_RST_
EN = = 1?
N
System reset
and SRS register
LPO
Osc
Alt Clock
Fast
Fn Test
Clock
WDOG
Clock
Selection
WDOG CLK
WDOG
reset count
WDOGEN = WDOG Enable
WINEN = Windowed Mode Enable
WDOGT = WDOG Time-out Value
WDOGCLKSRC = WDOG Clock Source
WDOG Test = WDOG Test Mode
WAIT EN = Enable in wait mode
STOP EN = Enable in stop mode
Standby EN = Enable in standby mode
Debug EN = Enable in debug mode
SRS = System Reset Status Register
R = Timer Reload
Figure 23-1. WDOG Operation
The preceding figure shows the operation of the watchdog. The values for N and K are:
• N = 256
• K = 20
The watchdog is a fail safe mechanism that brings the system into a known initial state in
case of its failure due to CPU clock stopping or a run away condition in code execution.
In its simplest form, the watchdog timer runs continuously off a clock source and expects
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
517