K60P100M100SF2RM Datasheet, PDF (111/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 3 Chip Configuration
Table 3-41. Reference links to related information (continued)
Topic
System memory map
Clocking
Transfers
Signal Multiplexing
Related module
Crossbar switch
Port control
Reference
System memory map
Clock Distribution
Crossbar switch
Signal Multiplexing
3.5.7.1 JTAG instruction
The system JTAG controller implements an EZPORT instruction. When executing this
instruction, the JTAG controller resets the core logic and asserts the EzPort chip select
signal to force the processor into EzPort mode.
3.5.7.2 Flash Option Register (FOPT)
The FOPT[EZPORT_DIS] bit can be used to prevent entry into EzPort mode during
reset. If the FOPT[EZPORT_DIS] bit is cleared, then the state of the chip select signal
(EZP_CS) is ignored and the MCU always boots in normal mode.
This option is useful for systems that use the EZP_CS/NMI signal configured for its NMI
function. Disabling EzPort mode prevents possible unwanted entry into EzPort mode if
the external circuit that drives the NMI signal asserts it during reset.
The FOPT register is loaded from the flash option byte. If the flash option byte is
modified the new value takes effect for any subsequent resets, until the value is changed
again.
3.5.8 FlexBus Configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
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