K60P100M100SF2RM Datasheet, PDF (155/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Peripheral
bridge
Register
access
Chapter 3 Chip Configuration
UART
Module signals
Topic
Full description
System memory map
Clocking
Power management
Signal Multiplexing
Figure 3-62. UART configuration
Table 3-73. Reference links to related information
Related module
UART
Port control
Reference
UART
System memory map
Clock Distribution
Power management
Signal Multiplexing
3.9.6.1 UART configuration information
This device contains five UART modules. This section describes how each module is
configured on this device.
1. Standard features of all UARTs:
• RS-485 support
• Hardware flow control (RTS/CTS)
• 9-bit UART to support address mark with parity
• MSB/LSB configuration on data
2. UART0 and UART1 are clocked from the core clock, the remaining UARTs are
clocked on the bus clock. The maximum baud rate is 1/16 of related source clock
frequency.
3. IrDA is available on all UARTs
4. UART0 contains the standard features plus ISO7816
5. AMR support on all UARTs. The pin control and interrupts (PORT) module supports
open-drain for all I/O.
6. UART0 and UART1 contains 8-entry transmit and 8-entry receive FIFOs
7. All other UARTs contain a 1-entry transmit and receive FIFOs
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
155