K60P100M100SF2RM Datasheet, PDF (725/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 29 External Bus Interface (FlexBus)
FB_CLK
FB_A[Y]
Address
FB_D[X]
Address
Data
FB_RW
FB_TS
FB_ALE
AA=1
FB_CSn
AA=0
FB_OEn
FB_BE/BWEn
FB_TA
AA=1
AA=0
FB_TSIZ[1:0]
TSIZ
Figure 29-39. Write-Bus Cycle (One Wait State)
29.4.6.4.2 Address Setup and Hold
The timing of the assertion and negation of the chip selects, byte selects, and output
enable can be programmed on a chip-select basis. Each chip-select can be programmed to
assert one to four clocks after transfer start/address-latch enable (FB_TS/FB_ALE) is
asserted. The following figures show read- and write-bus cycles with two clocks of
address setup respectively.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
725