K60P100M100SF2RM Datasheet, PDF (222/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

JTAG status and control registers
9.5.1 MDM-AP Control Register
Table 9-5. MDM-AP Control register assignments
Bit
Name
0 Flash Mass Erase in Progress
1 Debug Disable
2 Debug Request
3 System Reset Request
4 Core Hold Reset
5 VLLSx Debug Request
(VLLDBGREQ)
6 VLLSx Debug Acknowledge
(VLLDBGACK)
Secure¹
Description
Y
Set to cause mass erase. Cleared by hardware after mass erase
operation completes.
When mass erase is disabled (via MEEN and SEC settings), the erase
request does not occur and the Flash Mass Erase in Progress bit
continues to assert until the next system reset.
N
Set to disable debug. Clear to allow debug operation. When set it
overrides the C_DEBUGEN bit within the DHCSR and force disables
Debug logic.
N
Set to force the Core to halt.
If the Core is in a stop or wait mode, this bit can be used to wakeup
the core and transition to a halted state.
N
Set to force a system reset. The system remains held in reset until this
bit is cleared.
N
Configuration bit to control Core operation at the end of system reset
sequencing.
0 Normal operation - release the Core from reset along with the rest of
the system at the end of system reset sequencing.
1 Suspend operation - hold the Core in reset at the end of reset
sequencing. Once the system enters this suspended state, clearing
this control bit immediately releases the Core from reset and CPU
operation begins.
N
Set to configure the system to be held in reset after the next recovery
from a VLLSx mode. This bit drives directly to the Mode Controller to
control this feature.
This bit holds the Core in reset when VLLSx modes are exited to allow
the debugger time to re-initialize debug IP before the debug session
continues.
The Mode Controller captures this bit logic on entry to VLLSx modes.
Upon exit from VLLSx modes, the Mode Controller holds the Core in
reset at the end of system reset sequencing. The Mode Controller will
hold the Core in reset until VLLDBGACK is asserted.
The VLLDBGREQ bit clears automatically due to the POR reset
generated as part of the VLLSx recovery.
N
Set to release a Core being held in reset following a VLLSx recovery
This bit is used by the debugger to release the system reset when it is
being held on VLLSx mode exit. The debugger re-initializes all debug
IP and then assert this control bit to allow the Mode Controller to
release the Core from reset and allow CPU operation to begin.
The VLLDBGACK bit is cleared by the debugger or can be left set
because it clears automatically due to the POR reset generated as
part of the next VLLSx recovery.
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
222
Freescale Semiconductor, Inc.