K60P100M100SF2RM Datasheet, PDF (1324/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory Map/Register Definition
CANx_CTRL1 field descriptions (continued)
Field
Description
This bit configures FlexCAN to operate in Listen-Only Mode. In this mode, transmission is disabled, all
error counters are frozen and the module operates in a CAN Error Passive mode. Only messages
acknowledged by another CAN station will be received. If FlexCAN detects a message that has not been
acknowledged, it will flag a BIT0 error (without changing the REC), as if it was trying to acknowledge the
message.
Listen-Only Mode acknowledgement can be obtained by the state of ESR1[FLTCONF] field which is
Passive Error when Listen-Only Mode is entered. There can be some delay between the Listen-Only
Mode request and acknowledge.
This bit can only be written in Freeze mode as it is blocked by hardware in other modes.
2–0
PROPSEG
0 Listen-Only Mode is deactivated.
1 FlexCAN module operates in Listen-Only Mode.
Propagation Segment
This 3-bit field defines the length of the Propagation Segment in the bit time. The valid programmable
values are 0–7. This field can only be written in Freeze mode as it is blocked by hardware in other modes.
Propagation Segment Time = (PROPSEG + 1) * Time-Quanta.
Time-Quantum = one Sclock period.
48.3.4 Free Running Timer (CANx_TIMER)
This register represents a 16-bit free running counter that can be read and written by the
CPU. The timer starts from 0x0 after Reset, counts linearly to 0xFFFF, and wraps around.
The timer is clocked by the FlexCAN bit-clock (which defines the baud rate on the CAN
bus). During a message transmission/reception, it increments by one for each bit that is
received or transmitted. When there is no message on the bus, it counts using the
previously programmed baud rate. The timer is not incremented during Disable, Doze,
Stop and Freeze Modes.
The timer value is captured when the second bit of the identifier field of any frame is on
the CAN bus. This captured value is written into the Time Stamp entry in a message
buffer after a successful reception or transmission of a message.
If bit CTRL1[TSYN] is asserted the Timer is reset whenever a message is received in the
first available Mailbox, according to CTRL2[RFFN] setting.
The CPU can write to this register anytime. However, if the write occurs at the same time
that the Timer is being reset by a reception in the first Mailbox, then the write value is
discarded.
Reading this register affects the Mailbox Unlocking procedure; see Section "Message
Buffer Lock Mechanism".
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K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.