K60P100M100SF2RM Datasheet, PDF (1130/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Introduction
• Statistics information for received IP and protocol errors
• Configurable automatic discard of erroneous frames
• Configurable automatic host-to-network (RX) and network-to-host (TX) byte order
conversion for IP and TCP/UDP/ICMP headers within the frame
• Configurable padding remove for short IP datagrams on receive
• Configurable Ethernet payload alignment to allow for 32-bit word aligned header and
payload processing
• Programmable store-and-forward operation with clock and rate decoupling FIFOs
44.1.2.3 IEEE 1588 Features
• Support for all IEEE 1588 frames
• Reference clock can be chosen independently of the network speed
• Software-programmable precise time-stamping of ingress and egress frames
• Timer monitoring capabilities for system calibration and timing accuracy
management
• Precise time-stamping of external events with programmable interrupt generation
• Programmable event and interrupt generation for external system control
• Hardware- and software-controllable timer synchronization
• 4 channel IEEE 1588 timer, each with support for input capture and output compare
using the 1588 counter
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K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.