K60P100M100SF2RM Datasheet, PDF (70/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Core modules
Debug
Interrupts
SRAM
Upper
Crossbar
switch
SRAM
Lower
ARM Cortex-M4
PPB
Core
Figure 3-1. Core configuration
Table 3-1. Reference links to related information
Topic
Related module
Full description
ARM Cortex-M4 core,
r0p0
System memory map
Clocking
Power management
System/instruction/data
bus module
Crossbar switch
System/instruction/data
bus module
SRAM
Debug
IEEE 1149.1 JTAG
IEEE 1149.7 JTAG
(cJTAG)
Serial Wire Debug
(SWD)
ARM Real-Time Trace
Interface
Interrupts
Nested Vectored
Interrupt Controller
(NVIC)
Private Peripheral Bus Miscellaneous Control
(PPB) module
Module (MCM)
Private Peripheral Bus
(PPB) module
Memory-Mapped
Cryptographic
Acceleration Unit
(MMCAU)
Reference
http://www.arm.com
System memory map
Clock distribution
Power management
Crossbar switch
SRAM
Debug
NVIC
MCM
MMCAU
3.2.1.1 Buses, interconnects, and interfaces
The ARM Cortex-M4 core has four buses as described in the following table.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
70
Freescale Semiconductor, Inc.