K60P100M100SF2RM Datasheet, PDF (915/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Field
Chapter 38 Programmable Delay Block (PDB)
PDBx_IDLY field descriptions (continued)
Description
These bits specify the delay value to schedule the PDB interrupt. It can be used to schedule an
independent interrupt at some point in the PDB cycle. If enabled, a PDB interrupt is generated, when the
counter is equal to the IDLY. Reading these bits returns the value of internal register that is effective for
the current cycle of the PDB.
38.3.5 Channel n Control Register 1 (PDBx_CHC1)
Each PDB channel has one Control Register, CHnC1. The bits in this register control the
functionality of each PDB channel operation.
Addresses: PDB0_CH0C1 is 4003_6000h base + 10h offset = 4003_6010h
PDB0_CH1C1 is 4003_6000h base + 38h offset = 4003_6038h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
W
BB
TOS
EN
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PDBx_CHnC1 field descriptions
Field
31–24
Reserved
23–16
BB
Description
This read-only field is reserved and always has the value zero.
PDB Channel Pre-Trigger Back-to-Back Operation Enable
These bits enable the PDB ADC pre-trigger operation as back-to-back mode. Only lower M pre-trigger bits
are implemented in this MCU. Back-to-back operation enables the ADC conversions complete to trigger
the next PDB channel pre-trigger and trigger output, so that the ADC conversions can be triggered on
next set of configuration and results registers. Application code must only enable the back-to-back
operation of the PDB pre-triggers at the leading of the back-to-back connection chain.
15–8
TOS
0 PDB channel's corresponding pre-trigger back-to-back operation disabled.
1 PDB channel's corresponding pre-trigger back-to-back operation enabled.
PDB Channel Pre-Trigger Output Select
These bits select the PDB ADC pre-trigger outputs. Only lower M pre-trigger bits are implemented in this
MCU.
0 PDB channel's corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral
clock cycle after a rising edge is detected on selected trigger input source or software trigger is
selected and SWTRIG is written with 1.
1 PDB channel's corresponding pre-trigger asserts when the counter reaches the channel delay register
plus one peripheral clock cycle after a rising edge is detected on selected trigger input source or
software trigger is selected and SETRIG is written with 1.
7–0
PDB Channel Pre-Trigger Enable
EN
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
915